公开(公告)号：US20150287683A1

公开(公告)日：2015-10-08

申请号：US14596480

申请日：2015-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANG-JIN MOON ,  TAE-SEONG KIM ,  BYUNG-LYUL PARK ,  JAE-HWA PARK ,  SUK-CHUL BANG

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/544 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.

Abstract translation: 提供半导体器件和半导体封装。 半导体器件包括半导体器件，其包括具有第一侧和第二侧的半导体衬底。 包括内部电路的前侧结构设置在半导体衬底的第一侧上。 钝化层设置在半导体衬底的第二侧上。 通孔结构通过半导体衬底和钝化层。 背面导电图案设置在半导体衬底的第二侧上。 背面导电图案电连接到通孔结构。 在钝化层中设置对准凹陷区域。 绝缘对准图案设置在对准凹陷区域中。

公开(公告)号：US20180218966A1

公开(公告)日：2018-08-02

申请号：US15936019

申请日：2018-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  KWANG-JIN MOON ,  BYUNG-LYUL PARK ,  JIN-HO AN ,  ATSUSHI FUJISAKI

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L25/065 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

公开(公告)号：US20150129978A1

公开(公告)日：2015-05-14

申请号：US14326282

申请日：2014-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANG-JIN MOON ,  BYUNG-LYUL PARK ,  JAE-HWA PARK

IPC: H01L27/02 ,  H01L27/088 ,  H01L23/48

CPC classification number: H01L27/0296 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/088 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate.

Abstract translation: 半导体集成电路器件包括延伸穿过衬底的TSV（贯通硅通孔），邻近衬底第一表面的衬底中的第一阱，第一阱上的有源器件的栅极，充电保护阱和 充电保护门对充电保护良好。 充电保护孔设置在基板的与基板的第一表面相邻的基板中，插入在TSV孔和第一阱之间，并且包围TSV孔。 当TSV形成时，充电保护门防止有源器件的栅极被损坏，特别是当使用等离子体蚀刻工艺在衬底中形成TSV孔时。