公开(公告)号：US20190172512A1

公开(公告)日：2019-06-06

申请号：US16249594

申请日：2019-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok OH ,  Seong-Hwan JEON

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/021 ,  G11C29/028 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2207/108 ,  G11C2207/2254

Abstract: A method of operating a semiconductor memory device including a plurality of pins configured to transfer data and signals from/to an outside of the semiconductor memory device, a memory cell array and a control logic circuit to control access to the memory cell array. A write command synchronized with a main clock signal and data synchronized with a data clock signal are received from outside of the semiconductor memory device, the data is stored in the memory cell array based on a frequency-divided data clock signal, data is read from the memory cell array in response to a read command and a target address received from the outside of the semiconductor memory device, and the read data is transmitted to the outside of the semiconductor memory device selectively with a strobe signal generated based on a frequency of the main clock signal.

公开(公告)号：US20230273668A1

公开(公告)日：2023-08-31

申请号：US18144956

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Seok OH

IPC: G06F1/3234 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4074

CPC classification number: G06F1/3275 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4074

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

公开(公告)号：US20170308328A1

公开(公告)日：2017-10-26

申请号：US15492436

申请日：2017-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Young LIM ,  Ki-Seok OH ,  Sungyong SEO ,  Youngjin CHO ,  Insu CHOI

IPC: G06F3/06 ,  G11C11/406

Abstract: A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.

公开(公告)号：US20190163650A1

公开(公告)日：2019-05-30

申请号：US16006082

申请日：2018-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghyun KIM ,  Ki-Seok OH

IPC: G06F13/16 ,  G11C7/10 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/1678 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/4068 ,  G11C7/1075 ,  H01L25/0657 ,  H01L2225/06541

Abstract: An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.

公开(公告)号：US20180005686A1

公开(公告)日：2018-01-04

申请号：US15624491

申请日：2017-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok OH ,  Seong-Hwan JEON

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C29/52 ,  G11C11/4096 ,  G06F11/10

CPC classification number: G11C11/4076 ,  G06F11/1004 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411

Abstract: In a method of operating a semiconductor memory device including a memory cell array and a control logic circuit configured to control access to the memory cell array, data synchronized with a differential data clock signal is received from an external memory controller, the data is stored in the memory cell array based on a frequency-divided data clock signal from which the differential data clock signal is divided, data is read from the memory cell array in response to a read command and a target address from the memory controller, and the read data is transmitted to the memory controller with one of a single strobe signal and a differential strobe signal according to a strobe mode of the semiconductor memory device.

公开(公告)号：US20240361823A1

公开(公告)日：2024-10-31

申请号：US18764639

申请日：2024-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok OH

IPC: G06F1/3234 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F1/3275 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

公开(公告)号：US20210327476A1

公开(公告)日：2021-10-21

申请号：US17355765

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHUN LEE ,  Daesik MOON ,  Young-Soo SOHN ,  Young-Hoon SON ,  Ki-Seok OH ,  Changkyo LEE ,  Hyun-Yoon CHO ,  Kyung-Soo HA ,  Seokhun HYUN

IPC: G11C7/10 ,  G06F3/06

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US20210103328A1

公开(公告)日：2021-04-08

申请号：US15930732

申请日：2020-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Seok OH

IPC: G06F1/3234 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.