Semiconductor device having capacitor and method of fabricating the semiconductor device

    公开(公告)号:US09716094B2

    公开(公告)日:2017-07-25

    申请号:US15229424

    申请日:2016-08-05

    IPC分类号: H01L27/108 H01L49/02

    摘要: A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.

    SEMICONDUCTOR DEVICE HAVING CAPACITOR AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE

    公开(公告)号:US20170098652A1

    公开(公告)日:2017-04-06

    申请号:US15229424

    申请日:2016-08-05

    IPC分类号: H01L27/108 H01L49/02

    摘要: A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.

    CAPACITORS HAVING DIELECTRIC LAYERS WITH DIFFERENT BAND GAPS AND SEMICONDUCTOR DEVICES USING THE SAME
    4.
    发明申请
    CAPACITORS HAVING DIELECTRIC LAYERS WITH DIFFERENT BAND GAPS AND SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
    具有不同带扣的电介质层的电容器及使用其的半导体器件

    公开(公告)号:US20140231958A1

    公开(公告)日:2014-08-21

    申请号:US14070988

    申请日:2013-11-04

    IPC分类号: H01L49/02

    CPC分类号: H01L28/40 H01L27/1085

    摘要: A capacitor of a memory device includes dielectric layers with different energy band gaps. The capacitor may include, for example, a first electrode and a first dielectric layer on the first electrode. The capacitor may further include a second dielectric layer on the first dielectric layer. The first and second dielectric layers may include the same dielectric material with different concentration of an impurity therein. A second electrode is disposed on the second dielectric layer.

    摘要翻译: 存储器件的电容器包括具有不同能带隙的电介质层。 电容器可以包括例如第一电极和第一电极上的第一电介质层。 电容器还可以包括在第一电介质层上的第二电介质层。 第一和第二电介质层可以包括具有不同浓度的杂质的相同介电材料。 第二电极设置在第二电介质层上。

    Atomic layer deposition apparatus
    5.
    发明授权
    Atomic layer deposition apparatus 有权
    原子层沉积装置

    公开(公告)号:US08546270B2

    公开(公告)日:2013-10-01

    申请号:US13780560

    申请日:2013-02-28

    摘要: An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas.

    摘要翻译: 原子层沉积装置和原子层沉积方法提高了生产率。 原子层沉积装置包括反应室,用于在反应室内以给定间隔支撑多个半导体衬底并加热多个半导体衬底的加热器和分别位于反应室内并对应于多个半导体衬底的多个注射器 由加热器支撑的多个半导体基板。 多个喷射器分别扫过多个半导体基板上方喷射反应气体。