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    Methods of manufacturing a vertical memory device
    3.
    发明授权
    Methods of manufacturing a vertical memory device 有权

    公开(公告)号：US11063060B2

    公开(公告)日：2021-07-13

    申请号：US16454499

    申请日：2019-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Il-Woo Kim ,  Sang-Ho Rha ,  Byoung-Deog Choi ,  Ik-Soo Kim ,  Min-Jae Oh

    IPC: H01L21/8234 ,  H01L21/67 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/28

    Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

    Methods of Forming Wiring Structures and Methods of Fabricating Semiconductor Devices
    5.
    发明申请
    Methods of Forming Wiring Structures and Methods of Fabricating Semiconductor Devices 有权
    形成接线结构的方法和制造半导体器件的方法

    公开(公告)号：US20150194333A1

    公开(公告)日：2015-07-09

    申请号：US14516774

    申请日：2014-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woo-Kyung You ,  Sang-Ho Rha ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee

    IPC: H01L21/768

    CPC classification number: H01L21/7682 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76877

    Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.

    Abstract translation: 提供形成布线结构的方法包括在基板上形成绝缘中间层并在绝缘中间层上形成牺牲层。 牺牲层被部分地去除以限定多个开口。 在开口中形成接线图案。 通过等离子体处理将牺牲层转变成改性的牺牲层。 通过湿蚀刻工艺去除改性牺牲层。 在绝缘中间层上形成覆盖布线图案的绝缘层。 绝缘层在相邻布线图案之间限定了气隙。

    Methods of forming wiring structures and methods of fabricating semiconductor devices
    6.
    发明授权
    Methods of forming wiring structures and methods of fabricating semiconductor devices 有权
    形成布线结构的方法和制造半导体器件的方法

    公开(公告)号：US09390966B2

    公开(公告)日：2016-07-12

    申请号：US14516774

    申请日：2014-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woo-Kyung You ,  Sang-Ho Rha ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee

    IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/764

    CPC classification number: H01L21/7682 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76877

    Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.

    Abstract translation: 提供形成布线结构的方法包括在基板上形成绝缘中间层并在绝缘中间层上形成牺牲层。 牺牲层被部分地去除以限定多个开口。 在开口中形成接线图案。 通过等离子体处理将牺牲层转变成改性的牺牲层。 通过湿蚀刻工艺去除改性牺牲层。 在绝缘中间层上形成覆盖布线图案的绝缘层。 绝缘层在相邻布线图案之间限定了气隙。

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