公开(公告)号：US20220130767A1

公开(公告)日：2022-04-28

申请号：US17573421

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-kwan Ryu ,  Yun-seok Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip

公开(公告)号：US11081440B2

公开(公告)日：2021-08-03

申请号：US16563202

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yu-Kyung Park ,  Seung-kwan Ryu ,  Min-seung Yoon ,  Yun-seok Choi

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/538

Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

公开(公告)号：US20230275029A1

公开(公告)日：2023-08-31

申请号：US18144780

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-kwan Ryu ,  Yun-seok Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L23/5383 ,  H01L24/19

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US11676902B2

公开(公告)日：2023-06-13

申请号：US17573421

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-kwan Ryu ,  Yun-seok Choi

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L23/5383 ,  H01L24/19

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US11244904B2

公开(公告)日：2022-02-08

申请号：US16556538

申请日：2019-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-kwan Ryu ,  Yun-seok Choi

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US20180151362A1

公开(公告)日：2018-05-31

申请号：US15686578

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yool KANG ,  Kyoung-sil Park ,  Yun-seok Choi ,  Boo-deuk Kim ,  Ye-hwan Kim

IPC: H01L21/033 ,  H01L21/762

CPC classification number: H01L21/3081 ,  B05D1/005 ,  B05D3/0254 ,  B05D3/0272 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76224 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method of forming patterns for a semiconductor device includes preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, an aromatic ring-containing polymer, and a solvent, applying the hardmask composition to an etching target layer, forming a hardmask by heat-treating the applied hardmask composition, forming a photoresist pattern on the hardmask, forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask, and forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask.

公开(公告)号：US11996366B2

公开(公告)日：2024-05-28

申请号：US18144780

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-kwan Ryu ,  Yun-seok Choi

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L23/5383 ,  H01L24/19

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US10236185B2

公开(公告)日：2019-03-19

申请号：US15686578

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yool Kang ,  Kyoung-sil Park ,  Yun-seok Choi ,  Boo-deuk Kim ,  Ye-hwan Kim

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/762 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/108 ,  B05D1/00 ,  B05D3/02

Abstract: A method of forming patterns for a semiconductor device includes preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, an aromatic ring-containing polymer, and a solvent, applying the hardmask composition to an etching target layer, forming a hardmask by heat-treating the applied hardmask composition, forming a photoresist pattern on the hardmask, forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask, and forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask.

公开(公告)号：US20240274588A1

公开(公告)日：2024-08-15

申请号：US18641581

申请日：2024-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-kwan Ryu ,  Yun-seok Choi

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L21/565 ,  H01L21/568 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1815

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US11705391B2

公开(公告)日：2023-07-18

申请号：US17316028

申请日：2021-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yu-Kyung Park ,  Seung-kwan Ryu ,  Min-seung Yoon ,  Yun-seok Choi

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5384 ,  H01L25/18

Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.