公开(公告)号：US11081190B1

公开(公告)日：2021-08-03

申请号：US16881778

申请日：2020-05-22

Applicant: SanDisk Technologies LLC

Inventor： Abhinav Anand ,  Young Pil Kim ,  Dana Lee

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11582 ,  G11C11/56 ,  H01L27/11556

Abstract: A method for data recovery in a memory array of a non-volatile memory system, wherein the method comprises detecting an electrical short between a word line (WL) of a memory cell transistor and a local source line (LI) of a memory structure of the array, increasing an initial voltage bias at the local source line to a second voltage bias that exceeds a threshold voltage of the shorted memory cell transistor and a voltage level of a bit line of the memory structure, thereby causing a sensing current to flow in a direction from the local source line to the bit line, and sensing at a sense amplifier of the memory structure the sensing current.

公开(公告)号：US20180182771A1

公开(公告)日：2018-06-28

申请号：US15445579

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiying Costa ,  Daxin Mao ,  Christopher Petti ,  Dana Lee ,  Yao-Sheng Lee

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.

公开(公告)号：US09978456B2

公开(公告)日：2018-05-22

申请号：US14543660

申请日：2014-11-17

Applicant: SanDisk Technologies LLC

Inventor： Anubhav Khandelwal ,  Dana Lee ,  Abhijeet Manohar ,  Henry Chin ,  Gautam Dusija ,  Daniel Tuers ,  Chris Avila ,  Cynthia Hsu

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

公开(公告)号：US11810628B2

公开(公告)日：2023-11-07

申请号：US17673172

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： Jayavel Pachamuthu ,  Dana Lee

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3445 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

公开(公告)号：US20230260582A1

公开(公告)日：2023-08-17

申请号：US17673172

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： Jayavel Pachamuthu ,  Dana Lee

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

公开(公告)号：US10355007B2

公开(公告)日：2019-07-16

申请号：US15379927

申请日：2016-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiying Costa ,  Dana Lee ,  Yanli Zhang ,  Johann Alsmeier ,  Yingda Dong ,  Akira Matsudaira

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L29/788 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/1157

Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.

公开(公告)号：US20220399072A1

公开(公告)日：2022-12-15

申请号：US17347953

申请日：2021-06-15

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Dana Lee

IPC: G11C29/42 ,  G11C29/00 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells arranged along word lines. The one or more control circuits are configured to receive a plurality of encoded portions of data to be programmed in non-volatile memory cells of a target word line, each encoded portion of data encoded according to an Error Correction Code (ECC) encoding scheme, and arrange the plurality of encoded portions of data in a plurality of rows of data latches corresponding to a plurality of logical pages such that each encoded portion of data is distributed across two or more rows of data latches. The one or more control circuits are also configured to program the distributed encoded portions of data from the plurality of rows of data latches into non-volatile memory cells along a target word line.

公开(公告)号：US10558381B2

公开(公告)日：2020-02-11

申请号：US15381104

申请日：2016-12-16

Applicant: SanDisk Technologies LLC

Inventor： Henry Chin ,  Sateesh Desireddi ,  Dana Lee ,  Ashwin D T ,  Harshul Gupta ,  Parth Amin ,  Jia Li

IPC: G06F3/06

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

公开(公告)号：US10249382B2

公开(公告)日：2019-04-02

申请号：US15683602

申请日：2017-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dana Lee ,  Ekam Singh ,  Ashish Ghai ,  Kalpana Vakati

IPC: G11C11/34 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.

公开(公告)号：US20190066818A1

公开(公告)日：2019-02-28

申请号：US15683602

申请日：2017-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dana Lee ,  Ekam Singh ,  Ashish Ghai ,  Kalpana Vakati

IPC: G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.