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公开(公告)号：US20150221627A1
公开(公告)日：2015-08-06
申请号：US14576068
申请日：2013-09-25
Applicant: Sandia Corporation
Inventor： Gregory N. Nielson , Carlos Anthony Sanchez , Anna Tauke-Pedretti , Bonsang Kim , Jeffrey Cederberg , Murat Okandan , Jose Luis Cruz-Campa , Paul J. Resnick
IPC: H01L25/00 , H01L21/283 , H01L21/311 , H01L25/065 , H01L21/683
CPC classification number: H01L25/50 , B81C1/00373 , B81C2201/0194 , H01L21/283 , H01L21/31111 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L24/13 , H01L24/80 , H01L24/97 , H01L25/0657 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2221/68381 , H01L2224/0401 , H01L2224/08145 , H01L2224/13005 , H01L2224/131 , H01L2224/14135 , H01L2224/80006 , H01L2224/80896 , H01L2224/9202 , H01L2224/97 , H01L2225/06517 , H01L2225/06568 , H01L2224/11 , H01L2224/80001 , H01L2924/00012 , H01L2924/014
Abstract: An apparatus is disclosed that includes a first plurality of devices made of a group III-V semiconductor material and a second plurality of devices made of a semiconductor material different than the material of the first plurality of devices that are bonded to the first plurality of devices. The apparatus also includes a dielectric layer surrounding the first plurality of devices and the second plurality of devices to mechanically bond the first plurality of devices to the second plurality of devices.
Abstract translation: 公开了一种装置，其包括由III-V族半导体材料制成的第一多个器件和由与第一多个器件接合的第一多个器件的材料不同的半导体材料制成的第二多个器件 。 该装置还包括围绕第一多个装置的电介质层和第二多个装置，以将第一多个装置机械地结合到第二多个装置。
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公开(公告)号：US20140102520A1
公开(公告)日：2014-04-17
申请号：US13649238
申请日：2012-10-11
Applicant: Sandia Corporation
Inventor： Anna Tauke-Pedretti , Jeffrey Cederberg , Gregory N. Nielson , Murat Okandan , Jose Luis Cruz-Campa
CPC classification number: H01L31/043 , H01L31/0687 , H01L31/0693 , H01L31/1844 , Y02E10/544
Abstract: A microsystems-enabled multi-junction photovoltaic (MEM-PV) cell includes a first photovoltaic cell having a first junction, the first photovoltaic cell including a first semiconductor material employed to form the first junction, the first semiconductor material having a first bandgap. The MEM-PV cell also includes a second photovoltaic cell comprising a second junction. The second photovoltaic cell comprises a second semiconductor material employed to form the second junction, the second semiconductor material having a second bandgap that is less than the first bandgap, the second photovoltaic cell further comprising a first contact layer disposed between the first junction of the first photovoltaic cell and the second junction of the second photovoltaic cell, the first contact layer composed of a third semiconductor material having a third bandgap, the third bandgap being greater than or equal to the first bandgap.
Abstract translation: 具有微系统的多结光伏（MEM-PV）电池包括具有第一结的第一光伏电池，第一光伏电池包括用于形成第一结的第一半导体材料，第一半导体材料具有第一带隙。 MEM-PV电池还包括包含第二结的第二光伏电池。 所述第二光伏电池包括用于形成所述第二结的第二半导体材料，所述第二半导体材料具有小于所述第一带隙的第二带隙，所述第二光伏电池还包括第一接触层，所述第一接触层设置在所述第一 光电池和第二光伏电池的第二接头，第一接触层由具有第三带隙的第三半导体材料组成，第三带隙大于或等于第一带隙。
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3.发明授权Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction 有权通过蚀刻设置在半导体器件和衬底之间的分级组合物释放层来分离半导体器件与衬底，包括形成减少静电的突起公开(公告)号：US09029239B2
公开(公告)日：2015-05-12
申请号：US14067433
申请日：2013-10-30
Applicant: Sandia Corporation
IPC: H01L21/46 , H01L31/0735 , H01L31/18
CPC classification number: H01L31/18 , H01L21/7806 , H01L31/0735 , H01L31/1852 , H01L31/1892 , Y02E10/52 , Y02E10/544
Abstract: A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.
Abstract translation: 一种方法包括用蚀刻来蚀刻耦合在多个半导体器件和衬底之间的释放层。 蚀刻包括蚀刻半导体器件和衬底之间的释放层，直到半导体器件至少基本上从衬底上释放出来。 蚀刻还包括在每个半导体器件和衬底之间的剥离层中蚀刻突起。 在每个半导体器件和衬底之间保持突起的同时停止蚀刻。 该方法还包括从衬底分离半导体器件。 还公开了其它方法和装置。
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4.发明申请PHOTOVOLTAIC POWER GENERATION SYSTEM WITH PHOTOVOLTAIC CELLS AS BYPASS DIODES 有权具有光伏电池的光伏发电系统作为旁路二极管公开(公告)号：US20150114444A1
公开(公告)日：2015-04-30
申请号：US14061946
申请日：2013-10-24
Applicant: Sandia Corporation
Inventor： Anthony L. Lentine , Gregory N. Nielson , Anna Tauke-Pedretti , Joseq Luis Cruz-Campa , Murat Okandan
IPC: H01L31/05
CPC classification number: H01L31/05 , H01L31/042 , H01L31/044 , Y02E10/50
Abstract: A photovoltaic power generation system that includes a solar panel is described herein. The solar panel includes a photovoltaic sub-module, which includes a group of microsystem enabled photovoltaic cells. The group includes a first string of photovoltaic cells, a second string of photovoltaic cells, and a differing photovoltaic cell. Photovoltaic cells in the first string are electrically connected in series, and photovoltaic cells in the second string are electrically connected in series. Further, the first string of photovoltaic cells, the second string of photovoltaic cells, and the differing photovoltaic cell are electrically connected in parallel. Moreover, the differing photovoltaic cell is used as a bypass diode for the first string of photovoltaic cells and the second string of photovoltaic cells.
Abstract translation: 本文描述了包括太阳能电池板的光伏发电系统。 太阳能电池板包括光伏子模块，其包括一组支持微系统的光伏电池。 该组包括第一串光伏电池，第二串光伏电池和不同的光伏电池。 第一串中的光伏电池串联电连接，并且第二串中的光伏电池串联电连接。 此外，第一串光伏电池，第二串太阳能电池和不同的光伏电池并联电连接。 此外，不同的光伏电池用作第一串光伏电池和第二串光伏电池的旁路二极管。
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公开(公告)号：US09599781B1
公开(公告)日：2017-03-21
申请号：US14847806
申请日：2015-09-08
Applicant: Sandia Corporation
Inventor： Erik J. Skogen , Gregory A. Vawter , Anna Tauke-Pedretti
CPC classification number: G02B6/4206 , G02B6/12002 , G02B6/12004 , G02B6/1226 , G02B6/1228 , G02B6/14 , G02B6/264 , G02B6/4218
Abstract: The present invention relates to optical vias to optically connect multilevel optical circuits. In one example, the optical via includes a surface plasmon polariton waveguide, and a first optical waveguide formed on a first substrate is coupled to a second optical waveguide formed on a second substrate by the surface plasmon polariton waveguide. In some embodiments, the first optical waveguide includes a transition region configured to convert light from an optical mode to a surface plasmon polariton mode or from a surface plasmon polariton mode to an optical mode.
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Patent Agency Ranking
公开(公告)号：US09508881B2
公开(公告)日：2016-11-29
申请号：US13649238
申请日：2012-10-11
Applicant: Sandia Corporation
Inventor： Anna Tauke-Pedretti , Jeffrey Cederberg , Gregory N. Nielson , Murat Okandan , Jose Luis Cruz-Campa
IPC: H01L31/043 , H01L31/0687 , H01L31/0693 , H01L31/18
CPC classification number: H01L31/043 , H01L31/0687 , H01L31/0693 , H01L31/1844 , Y02E10/544
Abstract: A microsystems-enabled multi-junction photovoltaic (MEM-PV) cell includes a first photovoltaic cell having a first junction, the first photovoltaic cell including a first semiconductor material employed to form the first junction, the first semiconductor material having a first bandgap. The MEM-PV cell also includes a second photovoltaic cell comprising a second junction. The second photovoltaic cell comprises a second semiconductor material employed to form the second junction, the second semiconductor material having a second bandgap that is less than the first bandgap, the second photovoltaic cell further comprising a first contact layer disposed between the first junction of the first photovoltaic cell and the second junction of the second photovoltaic cell, the first contact layer composed of a third semiconductor material having a third bandgap, the third bandgap being greater than or equal to the first bandgap.
Abstract translation: 具有微系统的多结光伏（MEM-PV）电池包括具有第一结的第一光伏电池，第一光伏电池包括用于形成第一结的第一半导体材料，第一半导体材料具有第一带隙。 MEM-PV电池还包括包含第二结的第二光伏电池。 所述第二光伏电池包括用于形成所述第二结的第二半导体材料，所述第二半导体材料具有小于所述第一带隙的第二带隙，所述第二光伏电池还包括第一接触层，所述第一接触层设置在所述第一 光电池和第二光伏电池的第二接头，第一接触层由具有第三带隙的第三半导体材料组成，第三带隙大于或等于第一带隙。
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公开(公告)号：US08946052B2
公开(公告)日：2015-02-03
申请号：US13627425
申请日：2012-09-26
Applicant: Sandia Corporation
Inventor： Gregory N. Nielson , Carlos Anthony Sanchez , Anna Tauke-Pedretti , Bongsang Kim , Jeffrey Cederberg , Murat Okandan , Jose Luis Cruz-Campa , Paul J. Resnick
CPC classification number: H01L25/50 , B81C1/00373 , B81C2201/0194 , H01L21/283 , H01L21/31111 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L24/13 , H01L24/80 , H01L24/97 , H01L25/0657 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2221/68381 , H01L2224/0401 , H01L2224/08145 , H01L2224/13005 , H01L2224/131 , H01L2224/14135 , H01L2224/80006 , H01L2224/80896 , H01L2224/9202 , H01L2224/97 , H01L2225/06517 , H01L2225/06568 , H01L2224/11 , H01L2224/80001 , H01L2924/00012 , H01L2924/014
Abstract: A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.
Abstract translation: 一种方法包括在供体基底上形成释放层。 在剥离层上形成由第一半导体材料制成的多个器件。 在多个器件上形成第一介电层，使得多个器件的所有暴露表面被第一介电层覆盖。 所述多个装置化学地附接到由不同于第一半导体材料的第二半导体材料制成的接收装置，所述接收装置具有附接到与所述多个装置相对的所述接收装置的表面的接收基板。 蚀刻释放层以从多个装置释放施主衬底。 在多个装置和接收装置上施加第二介电层以将多个装置机械地附接到接收装置。
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公开(公告)号：US09929293B1
公开(公告)日：2018-03-27
申请号：US15479134
申请日：2017-04-04
Applicant: Sandia Corporation
Inventor： Jin K. Kim , John F. Klem , Eric A. Shaner , Benjamin Varberg Olson , Emil Andrew Kadlec , Anna Tauke-Pedretti , Torben Ray Fortune
IPC: H01L31/09 , H01L31/18 , H01L31/0352 , H01L31/0304 , H01L31/0224 , H01L31/109
CPC classification number: H01L31/035236 , H01L31/022408 , H01L31/03046 , H01L31/035281 , H01L31/109
Abstract: In a superlattice (SL) photodetector, each period of the SL includes first and second semiconductor layers having different compositions, at least one of which comprises indium arsenide (InAs). At least one of these two semiconductor layers has a graded composition. In embodiments, the first semiconductor layer comprises InAs and the second semiconductor layer is a graded layer comprising indium arsenide antimonide (InAsSb), wherein the antimony (Sb) concentration is varied. In examples, the Sb concentration in the second layer gradually increases from the top and bottom toward the middle of the layer.
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公开(公告)号：US20140084450A1
公开(公告)日：2014-03-27
申请号：US13627425
申请日：2012-09-26
Applicant: Sandia Corporation
Inventor： Gregory N. Nielson , Carlos Anthony Sanchez , Anna Tauke-Pedretti , Bongsang Kim , Jeffrey Cederberg , Murat Okandan , Jose Luis Cruz-Campa , Paul J. Resnick
CPC classification number: H01L25/50 , B81C1/00373 , B81C2201/0194 , H01L21/283 , H01L21/31111 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L24/13 , H01L24/80 , H01L24/97 , H01L25/0657 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2221/68381 , H01L2224/0401 , H01L2224/08145 , H01L2224/13005 , H01L2224/131 , H01L2224/14135 , H01L2224/80006 , H01L2224/80896 , H01L2224/9202 , H01L2224/97 , H01L2225/06517 , H01L2225/06568 , H01L2224/11 , H01L2224/80001 , H01L2924/00012 , H01L2924/014
Abstract: A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.
Abstract translation: 一种方法包括在供体基底上形成释放层。 在剥离层上形成由第一半导体材料制成的多个器件。 在多个器件上形成第一介电层，使得多个器件的所有暴露表面被第一介电层覆盖。 所述多个装置化学地附接到由不同于第一半导体材料的第二半导体材料制成的接收装置，所述接收装置具有附接到与所述多个装置相对的所述接收装置的表面的接收基板。 蚀刻释放层以从多个装置释放施主衬底。 在多个装置和接收装置上施加第二介电层以将多个装置机械地附接到接收装置。
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10.发明申请SEPARATING SEMICONDUCTOR DEVICES FROM SUBSTRATE BY ETCHING GRADED COMPOSITION RELEASE LAYER DISPOSED BETWEEN SEMICONDUCTOR DEVICES AND SUBSTRATE INCLUDING FORMING PROTUBERANCES THAT REDUCE STICTION 有权通过蚀刻分层组合物分离衬底中的半导体器件，在半导体器件和衬底之间进行处理，包括形成降低占位率的原子公开(公告)号：US20140048123A1
公开(公告)日：2014-02-20
申请号：US14067433
申请日：2013-10-30
Applicant: Sandia Corporation
IPC: H01L31/18 , H01L31/042
CPC classification number: H01L31/18 , H01L21/7806 , H01L31/0735 , H01L31/1852 , H01L31/1892 , Y02E10/52 , Y02E10/544
Abstract: A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.
Abstract translation: 一种方法包括用蚀刻来蚀刻耦合在多个半导体器件和衬底之间的释放层。 蚀刻包括蚀刻半导体器件和衬底之间的释放层，直到半导体器件至少基本上从衬底上释放出来。 蚀刻还包括在每个半导体器件和衬底之间的剥离层中蚀刻突起。 在每个半导体器件和衬底之间保持突起的同时停止蚀刻。 该方法还包括从衬底分离半导体器件。 还公开了其它方法和装置。
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