公开(公告)号：US20110123729A1

公开(公告)日：2011-05-26

申请号：US12917950

申请日：2010-11-02

申请人： Sang-Myoung Lee ,  Tae-Hyung Hwang ,  Jung-Woo Park ,  Kyung-Tae Chae ,  Hyung-Il Jeon ,  Seok-Joon Hong

发明人： Sang-Myoung Lee ,  Tae-Hyung Hwang ,  Jung-Woo Park ,  Kyung-Tae Chae ,  Hyung-Il Jeon ,  Seok-Joon Hong

IPC分类号： C09K19/00 ,  B32B37/02 ,  C23C14/34

CPC分类号： G02F1/133512 ,  B32B2309/105 ,  B32B2457/202 ,  G02F1/136286 ,  Y10T156/10 ,  Y10T428/1086

摘要： A display substrate includes a gate line disposed on a substrate, a data line crossing the gate line, a thin-film transistor electrically connected to the gate line and the data line, a light blocking layer disposed on the substrate and the thin-film transistor, where the light blocking layer blocks light and includes at least one selected from the group consisting of a zinc oxide, a copper oxide and a zinc-copper-oxide composite, and a pixel electrode electrically connected to the thin-film transistor.

摘要翻译： 显示基板包括设置在基板上的栅极线，与栅极线交叉的数据线，与栅极线和数据线电连接的薄膜晶体管，设置在基板上的遮光层和薄膜晶体管 其中遮光层阻挡光，并且包括从由氧化锌，氧化铜和氧化锌 - 铜 - 氧化物复合物组成的组中选择的至少一种以及与薄膜晶体管电连接的像素电极。

公开(公告)号：US08729551B2

公开(公告)日：2014-05-20

申请号：US13038545

申请日：2011-03-02

申请人： Nam-Seok Roh ,  Jung-Woo Park ,  Dae-Jin Park ,  Yu-Jin Kim ,  Joo-Han Bae ,  Tae-Hyung Hwang ,  Seok-Joon Hong

发明人： Nam-Seok Roh ,  Jung-Woo Park ,  Dae-Jin Park ,  Yu-Jin Kim ,  Joo-Han Bae ,  Tae-Hyung Hwang ,  Seok-Joon Hong

IPC分类号： H01L27/32 ,  H01L51/50

CPC分类号： G02F1/167 ,  G02B26/005

摘要： A flat panel display includes; a first substrate, a white reflective layer disposed on the first substrate, a pixel electrode disposed on the white reflective, a second substrate disposed facing the first substrate, a common electrode disposed on the second substrate, and an electrooptic layer disposed between the pixel electrode and the common electrode, wherein the white reflective layer includes at least one of TiO2 and BaSO4.

摘要翻译： 平板显示器包括： 第一基板，布置在第一基板上的白色反射层，设置在白色反射板上的像素电极，与第一基板相对配置的第二基板，设置在第二基板上的公共电极，以及设置在像素电极之间的电光层 和所述公共电极，其中所述白色反射层包括TiO 2和BaSO 4中的至少一种。

公开(公告)号：US20080081479A1

公开(公告)日：2008-04-03

申请号：US11824362

申请日：2007-06-29

申请人： Jung-Woo Park

发明人： Jung-Woo Park

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/32139

摘要： A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist pattern over an etch target layer, forming a first hard mask layer over a substrate structure, planarizing the first hard mask layer to form a first hard mask pattern and expose the first photoresist pattern, removing the first photoresist pattern, forming a second photoresist pattern enclosing the first hard mask pattern, forming a second hard mask layer over the substrate structure, planarizing the second hard mask layer to form a second hard mask pattern and expose the first hard mask pattern, removing the second photoresist pattern, and etching the etch target layer using the first hard mask pattern and the second hard mask pattern.

摘要翻译： 在半导体器件中制造精细图案的方法包括在蚀刻目标层上形成第一光致抗蚀剂图案，在衬底结构上形成第一硬掩模层，平面化第一硬掩模层以形成第一硬掩模图案，并将 第一光致抗蚀剂图案，去除第一光致抗蚀剂图案，形成包围第一硬掩模图案的第二光致抗蚀剂图案，在衬底结构上方形成第二硬掩模层，平坦化第二硬掩模层以形成第二硬掩模图案， 硬掩模图案，去除第二光致抗蚀剂图案，以及使用第一硬掩模图案和第二硬掩模图案蚀刻蚀刻目标层。

公开(公告)号：US07326587B2

公开(公告)日：2008-02-05

申请号：US11153746

申请日：2005-06-14

申请人： Jung-Woo Park ,  Jung-Min Ha

发明人： Jung-Woo Park ,  Jung-Min Ha

IPC分类号： H01L21/00

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/0745 ,  Y02E10/50

摘要： A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode. After forming the silicon germanium crystalline layer to a predefined thickness, a silicon crystalline layer can be further grown at the silicon germanium crystalline layer. After forming the silicon germanium crystalline layer and before forming the dielectric layer, annealing can be performed for a predefined time.

摘要翻译： 公开了一种具有电容器的半导体存储器件。 电容器包括由硅 - 锗晶体层形成的底部电容器表面或其中硅 - 锗晶体层覆盖硅晶体层的双层。 底部电容器表面是不均匀的，并且通常通过外延法形成。 硅锗晶体层的锗含量约为5-50％。 制造半导体存储器件的方法包括：在形成电容器底部电极的区域选择性地暴露晶体硅衬底的表面; 供应源气体以在选择性暴露的硅衬底的表面上生长硅锗晶体层; 在硅锗晶体层上堆叠介电层; 并在该电介质层上层叠导电层以形成电容器顶部电极。 在将硅锗晶层形成预定厚度之后，可以在硅锗晶层进一步生长硅晶层。 在形成硅锗晶层之后，在形成电介质层之前，可以进行预定时间的退火。

公开(公告)号：US20070182383A1

公开(公告)日：2007-08-09

申请号：US11647124

申请日：2006-12-28

申请人： Jung-Woo Park ,  Ki-Wook Lee ,  Dong-Wook Kim

发明人： Jung-Woo Park ,  Ki-Wook Lee ,  Dong-Wook Kim

IPC分类号： H02P9/00

CPC分类号： H02P9/46 ,  H02J3/386 ,  H02P9/007 ,  Y02E10/763

摘要： Disclosed herein is an electric power converting device and power converting method for controlling doubly-fed induction generators, which provides a synchronous generator for generating auxiliary electric power independently of a doubly-fed induction generator so as to generate electricity even in a system power-free environment, a grid-side converter is composed of a three-phase four-wire converter so as to generate a balanced voltage even in an unbalanced load condition and automatically synchronize a stator voltage of a doubly-fed induction generator and a system voltage with each other.

摘要翻译： 本发明公开了一种用于控制双馈感应发电机的电力转换装置和电力转换方法，其提供了一种用于独立于双馈感应发电机产生辅助电力的同步发电机，以便即使在无系统的系统中也能发电 电网侧转换器由三相四线转换器构成，即使在不平衡负载条件下也能产生平衡电压，并且自动同步双馈感应发电机的定子电压和系统电压 其他。

公开(公告)号：US20050230732A1

公开(公告)日：2005-10-20

申请号：US11153746

申请日：2005-06-14

申请人： Jung-Woo Park ,  Jung-Min Ha

发明人： Jung-Woo Park ,  Jung-Min Ha

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L31/0236 ,  H01L31/0745 ,  H01L27/14

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/0745 ,  Y02E10/50

摘要： A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode. After forming the silicon germanium crystalline layer to a predefined thickness, a silicon crystalline layer can be further grown at the silicon germanium crystalline layer. After forming the silicon germanium crystalline layer and before forming the dielectric layer, annealing can be performed for a predefined time.

摘要翻译： 公开了一种具有电容器的半导体存储器件。 电容器包括由硅 - 锗晶体层形成的底部电容器表面或其中硅 - 锗晶体层覆盖硅晶体层的双层。 底部电容器表面是不均匀的，并且通常通过外延法形成。 硅锗晶体层的锗含量约为5-50％。 制造半导体存储器件的方法包括：在形成电容器底部电极的区域选择性地暴露晶体硅衬底的表面; 供应源气体以在选择性暴露的硅衬底的表面上生长硅锗晶体层; 在硅锗晶体层上堆叠介电层; 并在该电介质层上层叠导电层以形成电容器顶部电极。 在将硅锗晶层形成预定厚度之后，可以在硅锗晶层进一步生长硅晶层。 在形成硅锗晶层之后，在形成电介质层之前，可以进行预定时间的退火。

公开(公告)号：US06835996B2

公开(公告)日：2004-12-28

申请号：US10684451

申请日：2003-10-15

申请人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

发明人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

IPC分类号： H01L2900

CPC分类号： H01L21/76224

摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

摘要翻译： 半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

公开(公告)号：US06577175B2

公开(公告)日：2003-06-10

申请号：US10041091

申请日：2002-01-07

申请人： Nam-Seog Kim ,  Jung-Woo Park

发明人： Nam-Seog Kim ,  Jung-Woo Park

IPC分类号： H03L706

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/0812

摘要： The invention relates to a semiconductor memory device and a method for generating an internal clock, the circuit of the semiconductor device including: a receiver for receiving an external clock; a delay compensation circuit for receiving an output of the receiver and delaying it by as much as the compensation delay time and control delay time subtracted out of a cycle of the external clock; an external control delay part for delaying an output of the delay compensation circuit by as much as the control delay time and unit increase/decrease delay time in response to an external control code; and an internal clock driver for driving an output of the external control delay part and generating an internal clock centered to externally applied data, thereby performing an accurate timing control to an external clock without loss of performance.

公开(公告)号：US06562707B2

公开(公告)日：2003-05-13

申请号：US10043942

申请日：2002-01-10

申请人： Jong-Ryol Ryu ,  Jung-Woo Park ,  Jung-Min Ha ,  Si-Young Choi

发明人： Jong-Ryol Ryu ,  Jung-Woo Park ,  Jung-Min Ha ,  Si-Young Choi

IPC分类号： H01L213205

CPC分类号： H01L29/66636 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/76879 ,  H01L29/7834

摘要： A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.

公开(公告)号：US07894034B2

公开(公告)日：2011-02-22

申请号：US12535547

申请日：2009-08-04

申请人： Jung-Woo Park

发明人： Jung-Woo Park

IPC分类号： G02F1/1345

CPC分类号： G09G3/006 ,  G09G2300/0426

摘要： A thin film transistor (TFT) array panel with improved contact between the display signal lines and test lines is presented. The TFT array panel includes: gate lines and data lines intersecting each other, switching elements connected to the gate lines and the data lines, and at least one test line disposed near end portions of the gate lines or the data lines. An insulating layer covers the gate lines, the data lines and the switching elements and has first contact holes exposing the end portions of the gate lines or the data lines and second contact holes exposing the test lines. Auxiliary test lines are formed on the insulating layer and commonly connected to conductive layers, wherein the conductive layers connect at least one test line to the gate lines or the data lines via the first and the second contact holes.

摘要翻译： 提出了一种具有改进的显示信号线和测试线之间接触的薄膜晶体管（TFT）阵列面板。 TFT阵列面板包括：彼此相交的栅极线和数据线，连接到栅极线和数据线的开关元件，以及设置在栅极线或数据线的端部附近的至少一条测试线。 绝缘层覆盖栅极线，数据线和开关元件，并且具有暴露栅极线或数据线的端部的第一接触孔和露出测试线的第二接触孔。 辅助测试线形成在绝缘层上并且共同连接到导电层，其中导电层经由第一和第二接触孔将至少一条测试线连接到栅极线或数据线。