公开(公告)号：US20160284806A1

公开(公告)日：2016-09-29

申请号：US14989485

申请日：2016-01-06

申请人： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

发明人： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L23/31 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/785

摘要： A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region n the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.

摘要翻译： 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构，栅极结构的侧壁上的栅极间隔物，栅极结构之间的有源图案的源极/漏极区域以及栅极结构之间的源极/漏极接触 并连接到源极/漏极区域。 源极/漏极接触包括在栅极结构之间并与栅极间隔物接触的第一部分，第一部分上的第二部分并且不与栅极间隔物接触，并且在第二部分上具有第三部分。 第二和第三部分之间的第一边界处于与栅极结构的顶表面基本相同的高度。

公开(公告)号：US09754880B2

公开(公告)日：2017-09-05

申请号：US15016376

申请日：2016-02-05

申请人： Jae-Jik Baek ,  Kee-Sang Kwon ,  Sang-Jine Park ,  Bo-Un Yoon

发明人： Jae-Jik Baek ,  Kee-Sang Kwon ,  Sang-Jine Park ,  Bo-Un Yoon

IPC分类号： H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L23/528 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/088 ,  H01L27/0886

摘要： The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.

公开(公告)号：US20160284699A1

公开(公告)日：2016-09-29

申请号：US15007882

申请日：2016-01-27

申请人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

发明人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L27/0886 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/6656

摘要： A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

摘要翻译： 提供半导体器件。 半导体器件包括限定衬底上的沟槽并包括上部和下部的栅极间隔物，栅极绝缘膜，其沿着沟槽的侧壁和底表面延伸并且不与所述沟槽的上部接触 栅极间隔物，沿着沟槽的侧壁和底面在栅极绝缘膜上延伸的下部导电膜，并且不与栅极间隔物的上部重叠，并且栅极绝缘的最上部的上部导电膜 在下导电膜上的膜。

公开(公告)号：US10128236B2

公开(公告)日：2018-11-13

申请号：US15007882

申请日：2016-01-27

申请人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

发明人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC分类号： H01L29/772 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

摘要： A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US08946026B2

公开(公告)日：2015-02-03

申请号：US13238284

申请日：2011-09-21

申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L21/8238 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

公开(公告)号：US20120129331A1

公开(公告)日：2012-05-24

申请号：US13238284

申请日：2011-09-21

申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L21/28

CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

公开(公告)号：US09461148B2

公开(公告)日：2016-10-04

申请号：US13799291

申请日：2013-03-13

申请人： Jae-Young Park ,  Ji-Hoon Cha ,  Jae-Jik Baek ,  Bon-Young Koo ,  Kang-Hun Moon ,  Bo-Un Yoon

发明人： Jae-Young Park ,  Ji-Hoon Cha ,  Jae-Jik Baek ,  Bon-Young Koo ,  Kang-Hun Moon ,  Bo-Un Yoon

IPC分类号： H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/66795

摘要： A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer on the surfaces of the first recesses; and expanding the first recesses into second recesses by removing the oxide layer. Related devices are also disclosed.

摘要翻译： 描述制造半导体器件的方法。 制造半导体器件的方法包括提供形成为从基板突出的翅片和形成在鳍片上的与栅极相交的多个栅电极; 在所述翅片的至少一个侧面上形成第一凹部; 在所述第一凹部的表面上形成氧化物层; 并且通过去除氧化物层将第一凹槽膨胀成第二凹陷。 还公开了相关设备。

公开(公告)号：US08652915B2

公开(公告)日：2014-02-18

申请号：US13212380

申请日：2011-08-18

申请人： Kevin Ahn ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Kevin Ahn ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/336

CPC分类号： H01L21/02532 ,  H01L21/0262 ,  H01L21/3083 ,  H01L29/66545 ,  H01L29/66636

摘要： A method of fabricating a semiconductor device can be provided by etching sidewalls of a preliminary trench in a substrate that are between immediately adjacent gate electrode structures, to recess the sidewalls further beneath the gate electrode structures to provide recessed sidewalls. Then, the recessed sidewalls and a bottom of the preliminary trench can be etched using crystallographic anisotropic etching to form a hexagonally shaped trench in the substrate.

摘要翻译： 半导体器件的制造方法可以通过蚀刻位于紧邻的栅电极结构之间的衬底中的预备沟槽的侧壁，从而在栅极电极结构之下进一步凹入侧壁以提供凹入的侧壁。 然后，可以使用晶体各向异性蚀刻来蚀刻预备沟槽的凹陷侧壁和底部，以在衬底中形成六边形形状的沟槽。

公开(公告)号：US08604550B2

公开(公告)日：2013-12-10

申请号：US13097409

申请日：2011-04-29

申请人： Kwang-Wook Lee ,  Jae-Jik Baek ,  In-Seak Hwang ,  Seok-Woo Nam

发明人： Kwang-Wook Lee ,  Jae-Jik Baek ,  In-Seak Hwang ,  Seok-Woo Nam

IPC分类号： H01L29/772

CPC分类号： H01L29/66545 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a semiconductor substrate having at least two oblique side surfaces and a first bottom surface in a recessed portion. A gate insulating layer is formed on the recessed portion. A gate electrode is formed on the gate insulating layer. A channel region is formed below the gate electrode. Gate spacers are formed on side surfaces of the gate electrode.

摘要翻译： 半导体器件包括具有至少两个倾斜侧表面和在凹陷部分中的第一底表面的半导体衬底。 在凹部上形成栅极绝缘层。 在栅极绝缘层上形成栅电极。 沟道区形成在栅电极的下方。 栅极间隔件形成在栅电极的侧表面上。

公开(公告)号：US20120049250A1

公开(公告)日：2012-03-01

申请号：US13191055

申请日：2011-07-26

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor integrated circuit device includes a substrate. A gate structure is formed on the substrate and includes a gate insulating film and a gate electrode. A first sidewall spacer is formed on two sidewalls of the gate structure. A second sidewall spacer is formed on the first sidewall spacer. A recess compensation film is interposed between the second sidewall spacer and the substrate. An epitaxial layer is in contact with the recess compensation film.

摘要翻译： 半导体集成电路器件包括衬底。 栅极结构形成在衬底上并且包括栅极绝缘膜和栅电极。 第一侧壁间隔件形成在栅极结构的两个侧壁上。 在第一侧壁间隔件上形成第二侧壁间隔物。 在第二侧壁间隔件和基板之间设置凹陷补偿膜。 外延层与凹部补偿膜接触。