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206 条记录 (耗时 0.038 秒)

    Power transducer
    1.
    发明授权
    Power transducer 有权
    功率传感器

    公开(公告)号：US08385078B2

    公开(公告)日：2013-02-26

    申请号：US12537281

    申请日：2009-08-07

    申请人： Satoshi Ibori ,  Yasushi Sasaki ,  Yutaka Maeno ,  Masayuki Hirota ,  Kazuyuki Fukushima

    发明人： Satoshi Ibori ,  Yasushi Sasaki ,  Yutaka Maeno ,  Masayuki Hirota ,  Kazuyuki Fukushima

    IPC分类号： H05K1/14

    CPC分类号： H05K7/02 ,  H01L2924/0002 ,  H02M7/003 ,  H05K1/0256 ,  H05K1/141 ,  H05K3/3447 ,  H05K7/1432 ,  H05K2201/10015 ,  H05K2201/10166 ,  H01L2924/00

    摘要： A power transducer is downsized by reducing the size of a power source board and highly reliable. The power source board is provided in the power transducer and for a large-current circuit. The power transducer includes a power semiconductor module having lead terminals. Of the lead terminals provided for the power semiconductor module and connected with the main circuit board, predetermined one or ones of the lead terminals is or are connected with the main circuit board in the vicinity of a main circuit terminal stage and at a position or positions lower than the main circuit terminal stage. Alternatively, predetermined one or ones of the lead terminals is or are connected with the main circuit board at a position or positions lower than a position at which the main circuit terminal stage is provided.

    摘要翻译： 功率传感器通过减小电源板的尺寸来缩小尺寸，并且可靠性高。 电源板设置在功率传感器和大电流电路中。 功率传感器包括具有引线端子的功率半导体模块。 在为功率半导体模块提供并与主电路板连接的引线端子中，预定的一个或多个引线端子与主电路板在主电路端子台附近或位置 低于主电路端子级。 或者，预定的一个或多个引线端子在主电路板上或与设置有主电路端子台的位置比较低的位置处连接。

    Semiconductor module, power converter using the same and manufacturing method thereof
    4.
    发明授权
    Semiconductor module, power converter using the same and manufacturing method thereof 有权
    半导体模块，使用该半导体模块的功率转换器及其制造方法

    公开(公告)号：US6144571A

    公开(公告)日：2000-11-07

    申请号：US506269

    申请日：2000-02-17

    申请人： Yasushi Sasaki ,  Yutaka Maeno ,  Hiroshi Fujii ,  Kinya Nakatsu ,  Toshio Ogawa ,  Akihiro Tamba ,  Kazuji Yamada

    发明人： Yasushi Sasaki ,  Yutaka Maeno ,  Hiroshi Fujii ,  Kinya Nakatsu ,  Toshio Ogawa ,  Akihiro Tamba ,  Kazuji Yamada

    IPC分类号： H02M7/04 ,  H01L25/16 ,  H02M7/48 ,  H05K1/14 ,  H03M7/00 ,  H01L23/043

    CPC分类号： H01L25/165 ,  H01L25/162 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/144

    摘要： In order to bring a moduled power converter into less size and cost in the case of a structure having a lead-insert-case, an insulated metal circuit board and a printed circuit board, a difficulty was encountered in thinning a wiring width and an increase in pad area for each metal wire has interfered with a reduction in its size and cost.In the present invention to cope with it, a power converter is constructed by using a semiconductor module having such a structure that a metal base and lead frames are adhered to each other in a state in which an insulating adhesive sheet is interposed therebetween, a resin-molded outer package is adhered to the metal base with an adhesive or the like, and a resin sealing agent is charged into the resin-molded outer package to thereby integrally seal the resin-molded outer package and circuit parts such as semiconductor elements implemented therein, whereby a reduction in size and cost thereof is realized.

    摘要翻译： 为了在具有引线插入壳体，绝缘金属电路板和印刷电路板的结构的情况下将模块化的功率转换器带入更小的尺寸和成本，在布线宽度变薄和增加时遇到困难 在每个金属线的焊盘区域中，其尺寸和成本受到干扰。 在本发明中，通过使用具有这样的结构的半导体模块来构成功率转换器，所述半导体模块具有金属基底和引线框架彼此粘合的状态，其间插入有绝缘粘合片，树脂 模塑的外包装用粘合剂等粘合到金属基底上，树脂密封剂装入树脂模塑的外包装中，从而将树脂模塑的外包装和其中实现的半导体元件的电路部件整体密封 从而实现了尺寸和成本的降低。

    Display driving circuit, display panel and display device
    6.
    发明授权
    Display driving circuit, display panel and display device 有权
    显示驱动电路，显示面板和显示设备

    公开(公告)号：US08970565B2

    公开(公告)日：2015-03-03

    申请号：US13378233

    申请日：2010-03-18

    申请人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

    发明人： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

    IPC分类号： G06F3/038 ,  G09G3/36 ,  G11C19/28

    CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/063

    摘要： A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.

    摘要翻译： 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。

    Signal processing circuit, inverter circuit, buffer circuit, level shifter, flip-flop, driver circuit, and display device
    7.
    发明授权
    Signal processing circuit, inverter circuit, buffer circuit, level shifter, flip-flop, driver circuit, and display device 有权
    信号处理电路，逆变电路，缓冲电路，电平转换器，触发器，驱动电路和显示装置

    公开(公告)号：US08779809B2

    公开(公告)日：2014-07-15

    申请号：US13819400

    申请日：2011-08-31

    申请人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    发明人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    IPC分类号： H03K3/00

    CPC分类号： H02J4/00 ,  H03K3/356008 ,  H03K3/356026 ,  H03K19/01714 ,  H03K19/01735 ,  Y10T307/50

    摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source. This configuration can increase reliability of a bootstrap-type signal processing circuit.

    摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 以及用于控制自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子，所述电荷控制部分和所述第一输出部分经由继电器部分彼此连接，用于任一 将电荷控制部和第一输出部彼此电连接，或者将电荷控制部和第一输出部彼此电阻塞，电荷控制部包括与第二电源连接的电阻。 该配置可以增加自举式信号处理电路的可靠性。

    Active matrix liquid crystal display device and method of driving the same
    8.
    发明授权
    Active matrix liquid crystal display device and method of driving the same 有权
    有源矩阵液晶显示装置及其驱动方法

    公开(公告)号：US08736534B2

    公开(公告)日：2014-05-27

    申请号：US11922491

    申请日：2006-07-11

    申请人： Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

    发明人： Etsuo Yamamoto ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2310/0245 ,  G09G2330/02 ,  G09G2330/027

    摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.

    摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的关断电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。

    Display driving circuit having a memory circuit, display device, and display driving method
    9.
    发明授权
    Display driving circuit having a memory circuit, display device, and display driving method 有权
    具有存储电路，显示装置和显示驱动方法的显示驱动电路

    公开(公告)号：US08547368B2

    公开(公告)日：2013-10-01

    申请号：US12734363

    申请日：2008-09-02

    申请人： Makoto Yokoyama ,  Yasushi Sasaki ,  Yuhichiroh Murakami

    发明人： Makoto Yokoyama ,  Yasushi Sasaki ,  Yuhichiroh Murakami

    IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/30 ,  G09G3/36

    CPC分类号： G09G3/3677 ,  G09G3/3655 ,  G09G2300/0876 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0219 ,  G11C19/184

    摘要： A display driving circuit of the present invention includes: a source driver (20) which outputs a source signal; a gate driver (30) which outputs a gate signal for turning on a switching element on a row; and a CS driver (40) which outputs a CS signal (CSOUT) whose electric potential is switched in a predetermined direction (low to high or high to low) in accordance with a polarity of the source signal. A CS driver (CSn) on an n-th row outputs a CS signal (CSOUT) to the n-th row in accordance with a gate signal (GLn) for the n-th row outputted from a gate driver (Gn) provided on the n-th row. This makes it possible to provide a display driving circuit which enables CC driving with a simple configuration.

    摘要翻译： 本发明的显示驱动电路包括：源极驱动器，其输出源极信号; 栅极驱动器（30），其输出用于导通行上的开关元件的栅极信号; 以及CS驱动器（40），其根据源极信号的极性输出电位从规定的方向（低到高或高到低）切换的CS信号（CSOUT）。 第n行的CS驱动器（CSn）根据从设置在第n行的栅极驱动器（Gn）输出的第n行的栅极信号（GLn）向第n行输出CS信号（CSOUT） 第n行。 这使得可以提供一种能够以简单的结构实现CC驱动的显示驱动电路。

    SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE
    10.
    发明申请
    SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE 有权
    信号处理电路，逆变器电路，缓冲电路，驱动电路，电平变换器和显示装置

    公开(公告)号：US20130194033A1

    公开(公告)日：2013-08-01

    申请号：US13819043

    申请日：2011-08-31

    申请人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    发明人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Etsuo Yamamoto

    IPC分类号： G05F3/16

    CPC分类号： G05F3/16 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2310/0291 ,  H04L25/0272

    摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.

    摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 用于控制所述自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子; 以及电阻器，其具有（i）连接到所述输出端子的第一端和（ii）连接到第二电源的第二端。 这种布置允许信号处理电路即使在自举效应已经磨损之后仍然保持输出电位。