公开(公告)号：US07799667B2

公开(公告)日：2010-09-21

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US20080293202A1

公开(公告)日：2008-11-27

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US20050001265A1

公开(公告)日：2005-01-06

申请号：US10864518

申请日：2004-06-10

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/763 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US20110073904A1

公开(公告)日：2011-03-31

申请号：US12923469

申请日：2010-09-23

申请人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

发明人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

摘要： A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.

摘要翻译： 半导体器件包括：SOI衬底; 半导体元件，其具有设置在所述SOI衬底的有源层中的第一和第二杂质层，所述第二杂质层围绕所述第一杂质层; 以及设置在与SOI衬底的嵌入式绝缘膜相邻的有源层的一部分中的多个第一和第二导电类型区域。 交替地布置第一和第二导电类型区域。 第一和第二导电类型区域具有对应于半导体元件的布局。

公开(公告)号：US06831331B2

公开(公告)日：2004-12-14

申请号：US09945621

申请日：2001-09-05

申请人： Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

发明人： Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/1087 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

摘要翻译： 提供具有功率晶体管结构的半导体器件。 功率晶体管结构包括独立地设置在半导体层的表面部分处的多个第一阱; 深部区域，其具有设置在所述第一阱之间的所述半导体层中的部分; 漏电极，连接到所述第一阱中的相应的漏极区; 源电极，其连接到第一阱中的各个源极区域和沟道阱区域，使得漏极电极或源极电极连接到感性负载; 以及连接构件，用于向深区域提供源极电位，其中当漏电极连接到感性负载时，连接构件可配置为连接到漏电极，并且当源电极连接到源电极时连接到源电极 表示感性负载。

公开(公告)号：US08604513B2

公开(公告)日：2013-12-10

申请号：US12923469

申请日：2010-09-23

申请人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

发明人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

IPC分类号： H01L29/66

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

摘要： A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.

摘要翻译： 半导体器件包括：SOI衬底; 半导体元件，其具有设置在所述SOI衬底的有源层中的第一和第二杂质层，所述第二杂质层围绕所述第一杂质层; 以及设置在与SOI衬底的嵌入式绝缘膜相邻的有源层的一部分中的多个第一和第二导电类型区域。 交替地布置第一和第二导电类型区域。 第一和第二导电类型区域具有对应于半导体元件的布局。

公开(公告)号：US06420281B2

公开(公告)日：2002-07-16

申请号：US09729778

申请日：2000-12-06

申请人： Takuya Okuno ,  Akira Yamada ,  Yoshiaki Nakayama

发明人： Takuya Okuno ,  Akira Yamada ,  Yoshiaki Nakayama

IPC分类号： H01L21324

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： One or more capacitors are formed using thermally oxidized films formed on a silicon layer of an SOI substrate. The capacitors may be formed alone or together with other semiconductor elements on a single SOI substrate. A diffuse layer having an impurity in a high density is first formed on the silicon layer, and then an oxidized film is formed on the diffused layer by thermal oxidation. Then, contaminants in the oxidized film are driven-out under a high temperature heat treatment, thereby to improve quality of the oxidized film, such as durability against a high voltage. Plural capacitors may be formed using oxidized films having a respectively different thickness, by repeating thermal oxidation and removal of the oxidized film.

摘要翻译： 使用形成在SOI衬底的硅层上的热氧化膜形成一个或多个电容器。 电容器可以单独形成或与单个SOI衬底上的其它半导体元件一起形成。 首先在硅层上形成具有高密度杂质的扩散层，然后通过热氧化在扩散层上形成氧化膜。 然后，在高温热处理下将氧化膜中的污染物排出，从而提高氧化膜的质量，例如耐高压的耐久性。 可以通过重复热氧化和去除氧化膜来形成具有不同厚度的氧化膜的多个电容器。

公开(公告)号：US07298020B2

公开(公告)日：2007-11-20

申请号：US10797081

申请日：2004-03-11

申请人： Syuji Asano ,  Yoshiaki Nakayama ,  Koji Eguchi

发明人： Syuji Asano ,  Yoshiaki Nakayama ,  Koji Eguchi

IPC分类号： H01L29/00

CPC分类号： H01L28/24 ,  H01L21/8221 ,  H01L27/0688

摘要： A wire (12) is formed on an insulating film (10) on a semiconductor substrate (1). The wire (12) is covered by silicon nitride film (14), inorganic SOG film (20) and TEOS film (21). A thin film resistance element (30) of chromium silicon (CrSi) is formed on the upper surface of the TEOS film (21). The acute angle (taper angle) at which a line connecting the local maximum and minimum points of a step on the upper surface of the TEOS film (21) beneath the area where the thin film resistance element (30) is formed intersects to the surface of the substrate (1) is set to 10° or less.

摘要翻译： 在半导体衬底（1）上的绝缘膜（10）上形成导线（12）。 线（12）由氮化硅膜（14），无机SOG膜（20）和TEOS膜（21）覆盖。 在TEOS膜（21）的上表面上形成有铬硅（CrSi）的薄膜电阻元件（30）。 连接薄膜电阻元件（30）形成区域下方的TEOS薄膜（21）的上表面上的台阶的局部最大值和最小点的线的锐角（锥角）与表面 的基板（1）设定为10°以下。

公开(公告)号：US6104076A

公开(公告)日：2000-08-15

申请号：US748896

申请日：1996-11-15

申请人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

发明人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

IPC分类号： H01L21/336 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L27/085 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L23/58

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

公开(公告)号：US5512357A

公开(公告)日：1996-04-30

申请号：US43973

申请日：1993-04-07

申请人： Kazuhiko Shimura ,  Yoshiaki Nakayama

发明人： Kazuhiko Shimura ,  Yoshiaki Nakayama

IPC分类号： D01D5/11 ,  D01F6/06 ,  D04H1/42 ,  D04H3/16 ,  B32B5/16 ,  D02G3/00 ,  D04H1/58

CPC分类号： D01F6/06 ,  D01D5/11 ,  D04H1/4291 ,  D04H1/4382 ,  D04H1/4391 ,  D04H3/16 ,  Y10T428/2924 ,  Y10T428/2927 ,  Y10T442/608

摘要： The present invention relates to a polypropylene three-dimensional plexifilamentary fiber, a method of manufacturing same, and a nonwoven fabric composed of the above fiber.The plexifilamentary fiber in accordance with the present invention has a three-dimensional plexifilamentary structure, and is characterized in that the fiber has a microwave birefringence of 0.07 or more. As a result, a dimensional stability under heating of the plexifilamentary fiber in accordance with the present invention is extremely high. Moreover, it is possible to obtain a plexifilamentary fiber having a high spreadability by adding a spreading agent to the plexifilamentary fiber. A nonwoven fabric made of such plexifilamentary fiber has a high thermal dimensional stability, and as a result, the nonwoven fabric in accordance with the present can be usefully used in a wrapping material having a heat resistance and air permeability, apparel having heat resistance and moisture permeability, a heat resistance paper, and engineering and building materials or the like.

摘要翻译： 聚丙烯三维丛状纤维及其制造方法技术领域本发明涉及聚丙烯三维丛状纤维，及其制造方法。 根据本发明的丛状纤维具有三维丛状结构，其特征在于，所述纤维的微波双折射为0.07以上。 结果，根据本发明的丛状纤维的加热下的尺寸稳定性非常高。 此外，通过向丛状纤维增加铺展剂，可以获得具有高铺展性的丛状纤维。 由这种丛状纤维制成的无纺布具有高的热尺寸稳定性，结果，根据本发明的无纺布可以有效地用于具有耐热性和透气性的包装材料，具有耐热性和水分的衣服 透气性，耐热性纸，以及工程和建筑材料等。