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    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
    4.
    发明授权
    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
    非平面半导体器件部分或完全缠绕在栅极电极和制造方法

    公开(公告)号：US07456476B2

    公开(公告)日：2008-11-25

    申请号：US10607769

    申请日：2003-06-27

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

    Nonplanar device with stress incorporation layer and method of fabrication
    6.
    发明授权
    Nonplanar device with stress incorporation layer and method of fabrication 有权
    具有应力结合层的非平面器件及其制造方法

    公开(公告)号：US07241653B2

    公开(公告)日：2007-07-10

    申请号：US11173443

    申请日：2005-06-30

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

    摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

    摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

    Method of forming sub-micron-size structures over a substrate
    9.
    发明授权
    Method of forming sub-micron-size structures over a substrate 失效
    在基底上形成亚微米级结构的方法

    公开(公告)号：US06887395B2

    公开(公告)日：2005-05-03

    申请号：US10364281

    申请日：2003-02-10

    申请人： Scott A. Hareland ,  Brian S. Doyle ,  Robert S. Chau

    发明人： Scott A. Hareland ,  Brian S. Doyle ,  Robert S. Chau

    IPC分类号： B44C1/22 ,  B81B1/00 ,  B81C1/00 ,  H01L21/00 ,  H01L29/06 ,  H01L29/12

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/0673 ,  Y10S438/947

    摘要： A method is provided for forming sub-micron-size structures over a substrate. A width-defining step is formed over the substrate. A width-defining layer is formed over an edge of the width-defining step. The width-defining layer is etched back to leave a spacer adjacent the width-defining step. A length-defining step is formed over the substrate. A length-defining layer is formed over an edge of the length-defining step. The length-defining layer is etched back to leave a spacer adjacent a first edge of the length-defining step and across a first portion of the spacer left by the width-defining layer. The length-defining step is then removed. The spacer left by the width-defining layer is then etched with the spacer left by the length-defining layer serving as a mask, to form the structure.

    摘要翻译： 提供了一种在衬底上形成亚微米级结构的方法。 在衬底上形成宽度限定步骤。 宽度限定层形成在宽度限定步骤的边缘上。 将宽度限定层回蚀刻以在宽度限定步骤附近留下间隔物。 在衬底上形成长度限定步骤。 长度限定层形成在长度限定步骤的边缘上。 长度限定层被回蚀刻以在与长度限定步骤的第一边缘相邻并且横跨由宽度限定层留下的间隔物的第一部分附近留下间隔物。 然后去除长度定义步骤。 然后由宽度限定层留下的间隔物用作为掩模的长度限定层留下的间隔物进行蚀刻，以形成结构。