公开(公告)号：US07514346B2

公开(公告)日：2009-04-07

申请号：US11297084

申请日：2005-12-07

申请人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

发明人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

IPC分类号： H01L21/4763

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

摘要翻译： 本发明是一种半导体器件，其包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 栅极电极形成在半导体本体的顶表面上的栅电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。

公开(公告)号：US07235809B2

公开(公告)日：2007-06-26

申请号：US11292911

申请日：2005-12-01

申请人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/06

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US07714397B2

公开(公告)日：2010-05-11

申请号：US11493789

申请日：2006-07-25

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L29/06

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

公开(公告)号：US07456476B2

公开(公告)日：2008-11-25

申请号：US10607769

申请日：2003-06-27

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

IPC分类号： H01L29/786

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

公开(公告)号：US07427794B2

公开(公告)日：2008-09-23

申请号：US11123565

申请日：2005-05-06

申请人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

发明人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

摘要翻译： 本发明是一种半导体器件，其包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 栅极电极形成在半导体本体的顶表面上的栅电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。

公开(公告)号：US07241653B2

公开(公告)日：2007-07-10

申请号：US11173443

申请日：2005-06-30

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L21/8238

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

公开(公告)号：US06970373B2

公开(公告)日：2005-11-29

申请号：US10679124

申请日：2003-10-02

申请人： Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott A. Hareland

发明人： Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott A. Hareland

IPC分类号： G11C11/412 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786 ,  G11C11/00

CPC分类号： G11C11/412 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

摘要翻译： 本发明是包括两个存取装置的CMOS SRAM单元，每个存取装置由具有单个鳍片的三栅晶体管组成; 两个上拉装置，每个上拉装置由具有单个鳍片的三栅极晶体管组成; 和两个下拉器件，每个下拉器件由具有多个鳍片的三栅晶体管组成。 还提供了一种用于制造包括双鳍三栅极晶体管的CMOS SRAM单元的方法。

公开(公告)号：US08405164B2

公开(公告)日：2013-03-26

申请号：US12767681

申请日：2010-04-26

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L29/06

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

公开(公告)号：US20110020987A1

公开(公告)日：2011-01-27

申请号：US12893753

申请日：2010-09-29

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

公开(公告)号：US20090061572A1

公开(公告)日：2009-03-05

申请号：US12259464

申请日：2008-10-28

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。