公开(公告)号：US06150713A

公开(公告)日：2000-11-21

申请号：US260471

申请日：1999-03-02

申请人： Se-chul Park ,  Kyu-han Lee ,  Ju-bong Kim ,  Sung-il Kang ,  Dong-il Shin ,  Bae-soon Jang

发明人： Se-chul Park ,  Kyu-han Lee ,  Ju-bong Kim ,  Sung-il Kang ,  Dong-il Shin ,  Bae-soon Jang

IPC分类号： H01L23/50 ,  H01L21/48 ,  H01L23/495

CPC分类号： H01L23/49582 ,  C25D5/16 ,  C25D5/18 ,  H01L21/4821 ,  H01L2224/48247 ,  H01L2224/85464 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14

摘要： A lead frame plating method including the steps of (a) forming an intermediate layer on the upper surface of a metal substrate, (b) submerging the metal substrate into a plating solution, and (c) forming a passive layer to a thickness of 0.01 to 1.5 microinches on the upper surface of the intermediate layer by applying a modulated current to the plating solution and the metal substrate.

摘要翻译： 一种引线框架电镀方法，包括以下步骤：（a）在金属基板的上表面上形成中间层，（b）将金属基板浸入电镀液中，（c）形成钝化层，厚度为0.01 通过向电镀溶液和金属基底施加调制电流至中间层的上表面上的1.5微英寸。

公开(公告)号：US06475646B2

公开(公告)日：2002-11-05

申请号：US09731766

申请日：2000-12-08

申请人： Se-chul Park ,  Dong-il Shin ,  Sung-il Kang ,  Sang-hoon Lee ,  Bae-soon Jang

发明人： Se-chul Park ,  Dong-il Shin ,  Sung-il Kang ,  Sang-hoon Lee ,  Bae-soon Jang

IPC分类号： B32B1520

CPC分类号： B32B15/00 ,  B32B15/018 ,  C25D5/34 ,  H01L21/4835 ,  H01L2924/0002 ,  Y10T428/12875 ,  Y10T428/12889 ,  Y10T428/1291 ,  Y10T428/12944 ,  Y10T428/12993 ,  H01L2924/00

摘要： A method for manufacturing a lead frame including the steps of electrocleaning the surface of a thin plate material, electropolishing the electrocleaned thin plate material, removing inclusions on the surface of the electropolished thin plate material, rinsing the inclusion-removed thin plate material with an acidic solution, and forming multi-plated layers on the rinsed material. The lead frame manufactured by the method has 5 or less inclusions each having approximately 1 &mgr;m, on the surface area of 1600 &mgr;m2, which impede a wire bonding property or solder wettability of the lead frame.

摘要翻译： 一种引线框架的制造方法，其特征在于，包括以下步骤：对薄板材料的表面进行电蒸镀，电解抛光电解薄板材料，去除电抛光薄板材料表面上的夹杂物，用酸性清洗夹杂物去除的薄板材料 溶液，并在冲洗后的材料上形成多层。 通过该方法制造的引线框架，在1600mum2的表面积上具有5个以下的含有约1个m的夹杂物，这阻碍了引线框架的引线接合性能或焊料润湿性。

公开(公告)号：US06469386B1

公开(公告)日：2002-10-22

申请号：US09492402

申请日：2000-01-27

申请人： Kyu-han Lee ,  Sang-hun Lee ,  Sung-il Kang ,  Se-chul Park

发明人： Kyu-han Lee ,  Sang-hun Lee ,  Sung-il Kang ,  Se-chul Park

IPC分类号： H01L2348

CPC分类号： C23C28/021 ,  C23C28/023 ,  C23C28/027 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48664 ,  H01L2224/49171 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075

摘要： A lead frame for a semiconductor package and a method for manufacturing the lead frame. In the manufacture of the lead frame, a protective layer is formed with nickel (Ni) or Ni alloy on a metal substrate, an intermediate layer is then formed with palladium (Pd) or Pd alloy on the protective layer. Then, Pd and gold (Au) are alternately plated on the surface of the intermediate layer to form an outermost layer including both Pd and Au particles thereon.

摘要翻译： 用于半导体封装的引线框架和用于制造引线框架的方法。 在引线框架的制造中，在金属基板上用镍（Ni）或Ni合金形成保护层，然后在保护层上用钯（Pd）或Pd合金形成中间层。 然后，将Pd和金（Au）交替地电镀在中间层的表面上，以形成其上包括Pd和Au颗粒的最外层。

公开(公告)号：US08110505B2

公开(公告)日：2012-02-07

申请号：US12466655

申请日：2009-05-15

申请人： Sung-il Kang ,  Chang-han Shim

发明人： Sung-il Kang ,  Chang-han Shim

IPC分类号： H01L21/311

CPC分类号： H01L21/4832 ,  H01L23/3107 ,  H01L23/49534 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.

摘要翻译： 提供引线框架，半导体封装以及制造引线框架和半导体封装件的方法。 引线框架包括：可安装半导体芯片的管芯焊盘; 形成在所述管芯焊盘的周围的多个引线图案; 填充蚀刻空间的绝缘有机材料，其插入在所述管芯焊盘和引线图案之间，并且结构地支撑所述管芯焊盘和所述引线图案; 以及形成在管芯焊盘的上表面和下表面上的预镀层和引线图案。

公开(公告)号：US20060282570A1

公开(公告)日：2006-12-14

申请号：US11498097

申请日：2006-08-03

申请人： Yoon-jick Lee ,  Sung-il Kang

发明人： Yoon-jick Lee ,  Sung-il Kang

IPC分类号： G06F3/00

CPC分类号： H04L12/40058 ,  G06F13/4282 ,  G06F2213/0012 ,  H04L12/5601 ,  H04L12/6418 ,  H04L2012/5665

摘要： A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous transfer to be terminated when the bus is in an idle state for a time interval which is larger than an isochronous gap period, (b) detecting a residual gap having a time interval which is larger than the time interval of an isochronous gap and smaller than the time interval of a subaction gap, (c) checking whether bandwidth for the transfer of isochronous data remains when the residual gap is detected in the step (b), and (d) transferring the isochronous data when it is determined that the bandwidth remains in the step (c). According to the variable isochronous data transfer method, it is possible to maximize the isochronous transfer by selectively using the residual bandwidth, which is assigned for the transfer of the isochronous data but is not used for the real transfer of the isochronous data, for the transfer of the isochronous data.

摘要翻译： 提供了一种用于传送可变等时数据的方法及其装置。 用于传送可变同步数据的方法包括以下步骤：（a）当总线处于空闲状态时确定等时间传输，时间间隔大于等时间隙周期，（b）检测具有 时间间隔大于同步间隙的时间间隔并小于子作用间隙的时间间隔;（c）在步骤（b）中检测到剩余间隙时是否检测同步数据的传送带宽是否保留， 以及（d）当确定所述带宽保留在步骤（c）中时，转移所述等时数据。 根据可变同步数据传输方法，可以通过选择性地使用被分配用于传送等时数据但不用于实时传送等时数据的剩余带宽来最大化等时传输，用于传送 的等时数据。

公开(公告)号：US08409726B2

公开(公告)日：2013-04-02

申请号：US12475764

申请日：2009-06-01

申请人： Chang-han Shim ,  Sung-il Kang ,  Se-chuel Park

发明人： Chang-han Shim ,  Sung-il Kang ,  Se-chuel Park

IPC分类号： B32B15/20

CPC分类号： H05K3/384 ,  C25D5/12 ,  H05K1/0346 ,  H05K1/0393 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T428/12514 ,  Y10T428/12861 ,  Y10T428/12868 ,  Y10T428/1291 ,  Y10T428/12944 ,  Y10T428/24917

摘要： Provided is a printed circuit board (PCB) with multiple metallic layers and a method of manufacturing the PCB to improve adhesion between a metal film and a polymer film, on which a circuit pattern is formed. The PCB includes: a first metal film; a polymer film formed on one surface of the first metal film; and a second metal film, interposed between the first metal film and the polymer film, having a first surface facing the first metal film and a second surface facing the polymer film, wherein the second surface is rougher than the first surface.

摘要翻译： 提供了具有多个金属层的印刷电路板（PCB）和制造PCB以提高金属膜和形成电路图案的聚合物膜之间的粘附性的方法。 PCB包括：第一金属膜; 形成在所述第一金属膜的一个表面上的聚合物膜; 以及介于所述第一金属膜和所述聚合物膜之间的第二金属膜，具有面向所述第一金属膜的第一表面和面向所述聚合物膜的第二表面，其中所述第二表面比所述第一表面更粗糙。

公开(公告)号：US08278564B2

公开(公告)日：2012-10-02

申请号：US12432898

申请日：2009-04-30

申请人： Chang-han Shim ,  Sung-il Kang ,  Se-chuel Park

发明人： Chang-han Shim ,  Sung-il Kang ,  Se-chuel Park

IPC分类号： H05K1/11 ,  H05K3/10

CPC分类号： H05K3/0038 ,  H05K3/244 ,  H05K3/384 ,  H05K3/427 ,  H05K2201/0112 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

摘要： Provided are a circuit board with a viahole and a method of manufacturing the same. The circuit board includes: a substrate formed of an insulating material; a conductive layer disposed on the substrate; a plated layer comprising nickel and disposed on the conductive layer; and a viahole passing through the substrate, the conductive layer, and the plated layer, wherein a crystal growth direction of nickel in the plated layer is parallel to a thickness-wise direction of the substrate.

摘要翻译： 提供一种具有通孔的电路板及其制造方法。 电路板包括：由绝缘材料形成的基板; 设置在所述基板上的导电层; 包含镍并设置在导电层上的镀层; 以及穿过基板，导电层和镀层的通孔，其中镀层中的镍的晶体生长方向平行于基板的厚度方向。

公开(公告)号：US06667987B1

公开(公告)日：2003-12-23

申请号：US09418442

申请日：1999-10-15

申请人： Min-jee Kwon ,  Sung-il Kang

发明人： Min-jee Kwon ,  Sung-il Kang

IPC分类号： H04J316

CPC分类号： H04L12/40058 ,  G06F13/385 ,  H04L12/40065 ,  H04L12/40071

摘要： A method of extending channels for the IEEE 1394 serial bus is provided. The method for extending channels of the IEEE 1394 serial bus in a channel assignment through an isochronous resource manager (IRM) of an IEEE 1394 node, wherein the node includes a CP register for physical channels and a CE register for extended channels which have the same format as the format of a CA register which holds information on channels assigned by the IRM, includes: checking whether all the channels of the IRM are used and there is available bandwidth; setting the value obtained by adding 64 to the value of the CP register, to the CE register when all the channels are used and there is available bandwidth; and generating a packet by setting a tag field value of a packet as a predetermined value when the value is set to the CE register. According to the present invention, it is possible to solve the shortage of the channels which can occur as the bandwidth increases. Namely, it is possible to prevent the incomplete use of bandwidth due to the restriction of the number of channels by increasing the 64 channels to up to 256 channels.

摘要翻译： 提供了一种扩展IEEE 1394串行总线的通道的方法。 用于通过IEEE 1394节点的同步资源管理器（IRM）在信道分配中扩展IEEE 1394串行总线的信道的方法，其中该节点包括用于物理信道的CP寄存器和具有相同的扩展信道的CE寄存器 格式为保存由IRM分配的信道的信息的CA寄存器的格式，包括：检查IRM的所有信道是否被使用，并且存在可用带宽; 将所有通道使用并具有可用带宽时，将通过将64个值添加到CP寄存器的值设置为CE寄存器; 并且当该值被设置为CE寄存器时，通过将分组的标签字段值设置为预定值来生成分组。 根据本发明，可以解决随着带宽增加而可能发生的信道的不足。 即，可以通过将64个通道增加到256个通道来防止由于通道数量的限制而带宽的不完全使用。

公开(公告)号：US07285845B2

公开(公告)日：2007-10-23

申请号：US11194285

申请日：2005-08-01

申请人： Sung-il Kang ,  Se-chuel Park

发明人： Sung-il Kang ,  Se-chuel Park

IPC分类号： H01L23/495

CPC分类号： H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48664 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599

摘要： A lead frame for a semiconductor package having not only high molding resin adhesiveness and a low delamination problem under a severe moisture absorbing atmosphere but also high interface adhesiveness and solder wettability of an Au wire, and a method of manufacturing the lead frame are provided. The lead frame includes a base metal layer formed of a metal and a plurality of plating layers having different components formed on at least a surface of the base metal layer, wherein the plating layers include, a Ni plating layer deposited on at least a surface of the base metal layer and formed of Ni or an Ni alloy, a Pd plating layer stacked on at least a surface of the Ni plating layer and formed of Pd or a Pd alloy, and a protection plating layer stacked on at least a surface of the Pd plating layer and formed of Au or an Au alloy, wherein the Ni plating layer is formed to have a predetermined a thickness and a surface coarseness.

摘要翻译： 提供了一种半导体封装的引线框架，其具有在严酷的吸湿气氛下不仅具有高模塑树脂粘合性和低分层问题，而且还提供了Au线的高界面粘合性和焊料润湿性，以及制造引线框架的方法。 引线框架包括由金属形成的基底金属层和在基底金属层的至少一个表面上形成的具有不同部件的多个镀层，其中镀层包括沉积在至少一个表面上的Ni镀层 由Ni或Ni合金形成的基底金属层，堆叠在Ni镀层的至少一个表面上并由Pd或Pd合金形成的Pd镀层，以及在该镀覆层的至少一个表面上堆叠的保护镀层 Pd镀层，由Au或Au合金形成，其中Ni镀层形成为具有预定厚度和表面粗糙度。

公开(公告)号：US08354741B2

公开(公告)日：2013-01-15

申请号：US13344126

申请日：2012-01-05

申请人： Sung-il Kang ,  Chang-han Shim

发明人： Sung-il Kang ,  Chang-han Shim

IPC分类号： H01L23/495

CPC分类号： H01L21/4832 ,  H01L23/3107 ,  H01L23/49534 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.

摘要翻译： 提供引线框架，半导体封装以及制造引线框架和半导体封装件的方法。 引线框架包括：可安装半导体芯片的管芯焊盘; 形成在所述管芯焊盘的周围的多个引线图案; 填充蚀刻空间的绝缘有机材料，其插入在所述管芯焊盘和引线图案之间，并且结构地支撑所述管芯焊盘和所述引线图案; 以及形成在管芯焊盘的上表面和下表面上的预镀层和引线图案。