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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170272079A1

    公开(公告)日：2017-09-21

    申请号：US15610705

    申请日：2017-06-01

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

    IPC: H03K19/177 ,  H03K19/173

    Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170263774A1

    公开(公告)日：2017-09-14

    申请号：US15604934

    申请日：2017-05-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI ,  Shuhei NAGATSUKA ,  Yutaka SHIONOIRI

    IPC: H01L29/786

    CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

    Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

    MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    4.
    发明申请
    MEMORY DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
    存储器件和半导体器件

    公开(公告)号：US20170033110A1

    公开(公告)日：2017-02-02

    申请号：US15292362

    申请日：2016-10-13

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

    IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

    Abstract translation: 本发明的目的是提供一种能够抑制功耗的存储器件和包括存储器件的半导体器件。 作为用作保持蓄积在用作存储元件的晶体管中的电荷的开关元件，为存储器件中的每个存储单元提供包括作为有源层的氧化物半导体膜的晶体管。 用作存储元件的晶体管具有第一栅电极，第二栅电极，位于第一栅电极和第二栅电极之间的半导体膜，位于第一栅电极和半导体膜之间的第一绝缘膜， 位于第二栅电极和半导体膜之间的第二绝缘膜，以及与半导体膜接触的源电极和漏电极。

    CIRCUIT SYSTEM
    6.
    发明申请
    CIRCUIT SYSTEM 有权
    电路系统

    公开(公告)号：US20150263007A1

    公开(公告)日：2015-09-17

    申请号：US14645566

    申请日：2015-03-12

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Yutaka OKAZAKI ,  Suguru HONDO

    IPC: H01L27/105 ,  H01L29/04 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L29/045 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

    Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

    Abstract translation: 提供一种具有良好电特性的晶体管的半导体器件。 半导体器件具有位于相同衬底上的存储器电路和电路。 存储电路包括电容器，第一晶体管和第二晶体管。 第一晶体管的栅极电连接到电容器和第二晶体管的源极和漏极之一。 电路包括串联电连接的第三晶体管和第四晶体管。 第一晶体管和第三晶体管各自包括含有硅的有源层，第二晶体管和第四晶体管各自包括包含氧化物半导体的有源层。

    Bootstrap Circuit and Semiconductor Device Having Bootstrap Circuit
    7.
    发明申请
    Bootstrap Circuit and Semiconductor Device Having Bootstrap Circuit 有权
    自举电路和具有自举电路的半导体器件

    公开(公告)号：US20150091629A1

    公开(公告)日：2015-04-02

    申请号：US14502209

    申请日：2014-09-30

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takahiko ISHIZU ,  Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tatsuya ONUKI

    IPC: H03K17/06

    CPC classification number: G11C5/145 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/785 ,  H01L29/7869 ,  H01L29/78696

    Abstract: A bootstrap circuit of which the capacitance of a bootstrap capacitor is small and which requires a shorter precharge period is provided. The bootstrap circuit includes transistors M41 and M42, capacitors BSC1 and BSC2, an inverter INV41, and keeper circuits 43 and 44. A signal OSG with a high voltage is generated from an input signal OSG_IN. As the signal OSG_IN is made a high level, a node SWG is made a high level by BSC1. After a signal BSE1 is made a high level and the node SWG is made a low level by the keeper circuit 44, a signal BSE2 is made a high level. By the capacitance coupling of BSC2, a voltage of an output terminal 22 increases.

    Abstract translation: 提供了一种自举电路，其自举电容器的电容小并且需要更短的预充电周期。 自举电路包括晶体管M41和M42，电容器BSC1和BSC2，反相器INV41和保持器电路43和44.从输入信号OSG_IN产生具有高电压的信号OSG。 当信号OSG_IN为高电平时，BSC1使节点SWG成为高电平。 在使信号BSE1成为高电平并且节点SWG被保持电路44为低电平之后，使信号BSE2成为高电平。 通过BSC2的电容耦合，输出端子22的电压增加。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20140367681A1

    公开(公告)日：2014-12-18

    申请号：US14474454

    申请日：2014-09-02

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka SHIONOIRI ,  Hidetomo KOBAYASHI

    IPC: G11C11/24 ,  H01L27/108 ,  H01L27/12

    CPC classification number: G11C11/24 ,  G11C11/005 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

    Abstract: The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.

    Abstract translation: 即使在非常短的时间断电或电源电压下降（例如断电或下垂）的情况下，易失性存储器中的数据也可能传统上会丢失。 鉴于上述情况，目的是即使使用用于高速数据处理的易失性存储器来延长数据保持时间。 数据保留时间可以通过备份存储在包括电容器和氧化物半导体晶体管的存储器中的易失性存储器中的数据内容来扩展。

    MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    9.
    发明申请
    MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220415893A1

    公开(公告)日：2022-12-29

    申请号：US17891248

    申请日：2022-08-19

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

    IPC: H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/13 ,  H01L27/115 ,  H01L29/786

    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

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