公开(公告)号：US20060156980A1

公开(公告)日：2006-07-20

申请号：US11321491

申请日：2005-12-29

申请人： Seok-jun Won ,  Yong-min Yoo ,  Dae-youn Kim ,  Young-hoon Kim ,  Dae-jin Kwon ,  Weon-hong Kim

发明人： Seok-jun Won ,  Yong-min Yoo ,  Dae-youn Kim ,  Young-hoon Kim ,  Dae-jin Kwon ,  Weon-hong Kim

IPC分类号： C23C16/00 ,  C03C25/68 ,  H01L21/306 ,  H01L21/302 ,  H01L21/31

CPC分类号： C23C16/45544 ,  C23C16/0272 ,  C23C16/403 ,  C23C16/405 ,  C23C16/4402 ,  C23C16/45561 ,  C23C16/45574 ,  H01L21/00 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/28562 ,  Y10T137/0318

摘要： An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

公开(公告)号：US20110097905A1

公开(公告)日：2011-04-28

申请号：US12980633

申请日：2010-12-29

申请人： Seok-jun Won ,  Yong-min Yoo ,  Dae-youn Kim ,  Young-hoon Kim ,  Dae-jin Kwon ,  Weon-hong Kim

发明人： Seok-jun Won ,  Yong-min Yoo ,  Dae-youn Kim ,  Young-hoon Kim ,  Dae-jin Kwon ,  Weon-hong Kim

IPC分类号： H01L21/31 ,  F17D1/00 ,  H01L21/20

CPC分类号： C23C16/45544 ,  C23C16/0272 ,  C23C16/403 ,  C23C16/405 ,  C23C16/4402 ,  C23C16/45561 ,  C23C16/45574 ,  H01L21/00 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/28562 ,  Y10T137/0318

摘要： An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

摘要翻译： 提供了一种通过改善气阀系统来防止发生死体积而制造使用具有改善吹扫效率的四通阀的半导体器件的装置和方法。 该装置包括反应室，处理基板以制造半导体器件; 第一处理气体供给管，其将第一处理气体供给到所述反应室中; 四通阀，具有第一入口，第二入口，第一出口和第二出口，并安装在第一处理气体供应管上，使得第一入口和第一出口连接到第一处理气体供应管; 连接到所述四通阀的第二入口的第二处理气体供给管，以供应第二处理气体; 连接到四通阀的第二出口的旁路; 和安装在旁路上的闸阀。

公开(公告)号：US07563672B2

公开(公告)日：2009-07-21

申请号：US11593670

申请日：2006-11-07

申请人： Dae-Jin Kwon ,  Jung-Min Park ,  Seok-Jun Won ,  Min-Woo Song ,  Weon-hong Kim ,  Ju-youn Kim

发明人： Dae-Jin Kwon ,  Jung-Min Park ,  Seok-Jun Won ,  Min-Woo Song ,  Weon-hong Kim ,  Ju-youn Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/016 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.

摘要翻译： 提供了包括金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件。 MIM电容器可以包括具有第一层和第二层的上电极。 上电极的第一层包括物理气相沉积（PVD）上电极，并且上电极的第二层在PVD上电极上包括离子化的PVD（IPVD）上电极。 还提供了相关方法。

公开(公告)号：US07407897B2

公开(公告)日：2008-08-05

申请号：US11173624

申请日：2005-07-01

申请人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L28/65 ,  Y10S438/957

摘要： In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

摘要翻译： 在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。 为了获得这些优点，在​​下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。 下电介质膜和上电介质膜可以由SiO 2组成。 中间电介质膜可以由HFO 2 N 2构成。

公开(公告)号：US20070111506A1

公开(公告)日：2007-05-17

申请号：US11593670

申请日：2006-11-07

申请人： Dae-Jin Kwon ,  Jung-Min Park ,  Seok-Jun Won ,  Min-Woo Song ,  Weon-hong Kim ,  Ju-youn Kim

发明人： Dae-Jin Kwon ,  Jung-Min Park ,  Seok-Jun Won ,  Min-Woo Song ,  Weon-hong Kim ,  Ju-youn Kim

IPC分类号： H01L21/4763

CPC分类号： H01L27/016 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.

摘要翻译： 提供了包括金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件。 MIM电容器可以包括具有第一层和第二层的上电极。 上电极的第一层包括物理气相沉积（PVD）上电极，并且上电极的第二层在PVD上电极上包括离子化的PVD（IPVD）上电极。 还提供了相关方法。

公开(公告)号：US20060017136A1

公开(公告)日：2006-01-26

申请号：US11173624

申请日：2005-07-01

申请人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L28/65 ,  Y10S438/957

摘要： In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

摘要翻译： 在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。 为了获得这些优点，在​​下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。 下电介质膜和上电介质膜可以由SiO 2组成。 中间电介质膜可以由HFO 2 N 2构成。

公开(公告)号：US20060163640A1

公开(公告)日：2006-07-27

申请号：US11339151

申请日：2006-01-25

申请人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

发明人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

IPC分类号： H01L29/94

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

摘要翻译： 在制造根据该方法制造的金属 - 绝缘体 - 金属（MIM）电容器和金属 - 绝缘体 - 金属（MIM））电容器的方法中，所述方法包括：在半导体衬底上形成绝缘层图案， 层图案具有分别限定要形成电容器单元的区域的多个开口; 在绝缘层图案和半导体衬底上形成下电极导电层; 形成填充所述下电极导电层上的开口的第一牺牲层; 在所述第一牺牲层上形成第二牺牲层; 平面化第二牺牲层; 暴露下电极导电层的上表面; 去除暴露的下电极导电层以形成彼此分离的多个下电极，每个相应于电容器单元; 并且在每个下电极上形成各自对应于电容器单元的电介质层和上电极，以提供构成相同电信号的一个电容器的多个MIM电容器单元。

公开(公告)号：US20060022245A1

公开(公告)日：2006-02-02

申请号：US11187489

申请日：2005-07-22

申请人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  H01L21/02172 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/0805 ,  H01L28/56

摘要： An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.

摘要翻译： 提供了能够减小施加电压对电容的影响的模拟电容器和制造模拟电容器的方法。 模拟电容器包括形成在基板上的下电极，包括至少一个氧化物层和至少一个氧氮化物层的多层电介质层，所述至少一个氧氮化物层由选自Hf，Al，Zr La，Ba，Sr，Ti，Pb，Bi及其组合形成在下电极上，形成在多层电介质层上的上电极。

公开(公告)号：US20060158829A1

公开(公告)日：2006-07-20

申请号：US11335411

申请日：2006-01-19

申请人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

发明人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

IPC分类号： H01G4/20

CPC分类号： H01G4/10 ,  H01G4/20

摘要： Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

公开(公告)号：US07732296B2

公开(公告)日：2010-06-08

申请号：US11339151

申请日：2006-01-25

申请人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

发明人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

IPC分类号： H01L21/20

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

摘要翻译： 在制造根据该方法制造的金属 - 绝缘体 - 金属（MIM）电容器和金属 - 绝缘体 - 金属（MIM））电容器的方法中，所述方法包括：在半导体衬底上形成绝缘层图案， 层图案具有分别限定要形成电容器单元的区域的多个开口; 在绝缘层图案和半导体衬底上形成下电极导电层; 形成填充所述下电极导电层上的开口的第一牺牲层; 在所述第一牺牲层上形成第二牺牲层; 平面化第二牺牲层; 暴露下电极导电层的上表面; 去除暴露的下电极导电层以形成彼此分离的多个下电极，每个相应于电容器单元; 并且在每个下电极上形成各自对应于电容器单元的电介质层和上电极，以提供构成相同电信号的一个电容器的多个MIM电容器单元。