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公开(公告)号：US20050153520A1
公开(公告)日：2005-07-14
申请号：US10887258
申请日：2004-07-08
IPC分类号： H01L21/308 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11543 , H01L21/823462 , H01L27/105 , H01L27/11526
摘要： The present invention discloses a method for forming an element isolation film of a semiconductor device, comprising the steps of: sequentially forming a pad oxide film, a pad nitride film and a mask oxide film on a semiconductor substrate on which a first region for forming a high voltage device and a second region for forming a low voltage device or a flash memory cell are defined; etching the mask oxide film, the pad nitride film and the pad oxide film in the first region and the mask oxide film in the second region, and forming an oxide film for the high voltage device in the first region; removing the residual pad nitride film in the second region; removing the nitride film and partially removing the oxide film for the high voltage device in the first region, wherein the oxide film for the high voltage device has a third thickness; removing the residual pad oxide film in the second region; partially removing the oxide film for the high voltage device in the first region according to a cleaning process, wherein the oxide film for the high voltage device has a third thickness; and forming a tunnel oxide film over the resulting structure, wherein a gate oxide film for a high voltage device including the oxide film for the high voltage device and the tunnel oxide film is formed in the first region, and the tunnel oxide film for the low voltage device and cell is formed in the second region.
摘要翻译： 本发明公开了一种形成半导体器件的元件隔离膜的方法，包括以下步骤：在半导体衬底上依次形成衬垫氧化膜，衬垫氮化物膜和掩模氧化物膜，在半导体衬底上形成第一区域 定义高压装置和用于形成低电压装置或闪存单元的第二区域; 在所述第一区域中蚀刻所述掩模氧化膜，所述衬垫氮化物膜和所述衬垫氧化物膜，并且在所述第二区域中蚀刻所述掩模氧化物膜，并且在所述第一区域中形成用于所述高电压器件的氧化物膜; 去除所述第二区域中的所述残留的衬垫氮化物膜; 去除所述氮化物膜并部分地去除所述第一区域中的所述高电压器件的氧化物膜，其中所述高压器件的氧化物膜具有第三厚度; 去除所述第二区域中的残余衬垫氧化物膜; 根据清洁过程，部分去除第一区域中的高电压器件的氧化膜，其中用于高压器件的氧化物膜具有第三厚度; 并在所得到的结构上形成隧道氧化膜，其中在第一区域中形成用于包括用于高压器件的氧化物膜和隧道氧化物膜的高电压器件的栅极氧化膜，并且用于低电压的隧道氧化物膜 电压装置和电池形成在第二区域中。
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公开(公告)号：US20050106822A1
公开(公告)日：2005-05-19
申请号：US10745008
申请日：2003-12-23
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： Disclosed is a method of manufacturing a flash memory device. In a flash memory device using a SA-STI scheme, a trench for isolation is buried with oxide. A field oxide film is then formed by means of a polishing process. Next, field oxide films of a cell region and a low-voltage transistor region are selectively etched by a given thickness. As EFH values of the cell region, the low-voltage transistor region and the high-voltage transistor region become same or similar, it is possible to secure stability of a subsequent process.
摘要翻译： 公开了一种制造闪速存储器件的方法。 在使用SA-STI方案的闪存器件中，用氧化物掩埋用于隔离的沟槽。 然后通过抛光工艺形成场氧化膜。 接下来，选择性地蚀刻单元区域和低电压晶体管区域的场氧化物膜的给定厚度。 作为单元区域的EFH值，低电压晶体管区域和高压晶体管区域变得相同或相似，可以确保后续处理的稳定性。
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公开(公告)号：US20060250049A1
公开(公告)日：2006-11-09
申请号：US11259199
申请日：2005-10-27
IPC分类号： H01L41/053
CPC分类号： H03H9/1085 , H01L2224/16225 , H03H9/059
摘要： The present invention provides a SAW device package used in filters, duplexers, etc., in particular, which simplifies sealing process for protecting the active area of a SAW device. The SAW device package comprises a wiring substrate, as a package base having connection patterns, having bare chip attaching means. A bare chip is flip-bonded and attached to the attaching means on the wiring substrate while maintaining the airtight condition. A resin molding part covers the top of the bare chip to seal the device. The invention facilitates maintaining an airtight condition of the active area which affects the operational characteristics of the device, and simplifies the manufacturing processes. Furthermore, the improved structure of the wiring substrate blocks the external moisture permeation, thereby enabling the device to better withstand the external changes.
摘要翻译： 本发明提供了一种特别用于滤波器，双工器等中的SAW器件封装，其简化了用于保护SAW器件的有源区域的密封工艺。 SAW器件封装包括布线衬底，作为具有连接图案的封装基座，具有裸芯片附接装置。 在保持气密状态的同时，将裸芯片翻转接合并附接到布线基板上的附接装置。 树脂成型部分覆盖裸芯片的顶部以密封装置。 本发明有助于维持影响装置的操作特性的活性区域的气密状态，并且简化了制造过程。 此外，布线基板的改进的结构阻止外部水分渗透，从而使得该装置能够更好地承受外部变化。
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4.发明申请公开(公告)号：US20060249824A1
公开(公告)日：2006-11-09
申请号：US11217465
申请日：2005-09-02
IPC分类号： H01L23/02
CPC分类号： H03H9/1085 , H01L24/97 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/48091 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/3025 , H03H3/08 , H03H9/059 , H03H9/1078 , H01L2224/81 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs.
摘要翻译： 这里公开了一种堆叠型表面声波封装。 表面声波封装包括具有形成在其上的多个电极的第一裸芯片，具有形成在其上的多个电极和通孔的第二裸芯片，将第一裸芯片电连接到第二裸芯片的上表面的连接部分 裸芯片，使得第一裸芯片的电极面对第二裸芯片的电极;以及密封构件，设置在第一裸芯片和第二裸芯片上，以在第一和第二裸芯片之间的操作表面上形成气密空间 。 表面声波封装可以防止在包装过程中由于外界的热冲击而引起的变形，提高产品的可靠性，最小化产品尺寸，并通过减少部件数量和材料成本降低制造成本。
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公开(公告)号：US20060141725A1
公开(公告)日：2006-06-29
申请号：US11129776
申请日：2005-05-16
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/42324 , H01L29/66825
摘要： A method of manufacturing a flash memory device wherein before an insulating film spacer of a contact region is removed after a gate line and source/drain are formed, a high quality buffer oxide film formed between the gate line and the insulating film spacer is made dense by means of an annealing process. Abnormal oxidization is thus prevented from occurring due to an exposed metal layer in a gate when the insulating film spacer is removed as at least part of the buffer oxide remains after the spacer is removed.
摘要翻译： 一种制造闪存器件的方法，其中在形成栅极线和源极/漏极之后去除接触区域的绝缘膜间隔物之前，形成在栅极线和绝缘膜间隔物之间的高质量缓冲氧化膜被制成密集 通过退火工艺。 因此，当绝缘膜间隔物被去除时，防止在栅极中暴露的金属层发生异常氧化，因为至少部分缓冲氧化物在除去间隔物后残留。
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公开(公告)号：US20050277251A1
公开(公告)日：2005-12-15
申请号：US10887260
申请日：2004-07-08
IPC分类号： H01L27/115 , H01L21/331 , H01L21/8239 , H01L21/8247
CPC分类号： H01L27/11539 , H01L27/11526 , H01L27/11536 , H01L27/11541 , H01L27/11543
摘要： Provided relates to a method of a flash memory device, which performs a first rapid thermal oxidation process at a H2 rich atmosphere for recovering an etched damage during a gate forming process, and performs a second rapid thermal oxidation process at the H2 rich atmosphere for ion-activating after performing an ion implantation process for forming a cell transistor junction and a peripheral circuit transistor junction. As a result of those processes, a Si-dangling bond cut off during a gate etching process has a Si—H combination structure and the whole processing time is reduced, and thus an abnormal oxidation caused at an edge of an ONO layer and a tunnel oxide film, which can make it possible to prevent a smiling phenomena of the ONO layer and a bird's beak phenomena of the tunnel oxide film.
摘要翻译： 本发明涉及一种闪存器件的方法，其在H 2富含气氛下进行第一快速热氧化处理，以在栅极形成工艺期间回收蚀刻损伤，并执行第二快速热氧化 在进行用于形成单元晶体管结的离子注入工艺和外围电路晶体管结的离子激活之后，在富H 2气氛下进行离子激活。 作为这些工艺的结果，在栅极蚀刻工艺期间切断的Si-悬挂键具有Si-H组合结构，并且整个处理时间减少，因此在ONO层和隧道的边缘处引起异常氧化 氧化膜，能够防止ONO层的微笑现象和隧道状氧化膜的鸟喙现象。
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公开(公告)号：US20060194370A1
公开(公告)日：2006-08-31
申请号：US11328197
申请日：2006-01-10
CPC分类号： H03H9/1078 , H01L24/97 , H01L2224/16 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/3025 , H03H9/0542 , H03H9/059 , H03H9/1085 , H05K1/0237 , H05K1/0306 , H05K1/181 , H05K3/284 , H05K2201/10083 , H05K2201/10636 , Y02P70/611 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： The present invention relates to a RF module and a fabrication method thereof, wherein the packaging steps of a SAW component and a module is carried out simultaneously, thereby simplifying the fabrication process and reducing the size of the module. In the invention, a chip component is mounted on a substrate having component-connecting patterns thereon, and a SAW component in a bare chip is flip-bonded to the substrate. Thereafter, the SAW component is selectively laminated with a film and then molded; or the SAW component and the chip component are laminated as a whole and metal-plated, without any molding; or a metal wall is disposed between the substrate and the SAW component and then molded. As a result, this reduces the size of the RF modules, and simplifies the fabrication process, thereby benefiting from a cost-saving effect.
摘要翻译： RF模块及其制造方法技术领域本发明涉及RF模块及其制造方法，其中SAW组件和模块的封装步骤同时进行，从而简化了制造工艺并减小了模块的尺寸。 在本发明中，芯片部件安装在其上具有部件连接图案的基板上，裸芯片中的SAW部件被翻转接合到基板。 然后，将SAW成分选择性地层压成膜，然后成型; 或者将SAW部件和芯片部件作为整体进行层叠而进行金属镀覆而不进行任何成形。 或者金属壁设置在基板和SAW部件之间，然后模制。 结果，这减小了RF模块的尺寸，并且简化了制造工艺，从而从成本节约的效果中获益。
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公开(公告)号：US20050142764A1
公开(公告)日：2005-06-30
申请号：US10878173
申请日：2004-06-28
IPC分类号： H01L21/316 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L21/823462 , H01L27/11526 , H01L27/11534
摘要： The present invention discloses a method for manufacturing a semiconductor device which forms a thick gate oxide film in a high voltage region and a thin tunnel oxide film in a cell region. The method for manufacturing the semiconductor device reduces a process time and improves uniformity of the gate oxide film in the high voltage region, by growing the gate oxide film in the high voltage region at a thickness of about 400 Å, and removing a residual nitride film in the cell region by performing an etching process using a BOE solution and an etching process using H3PO4 for 120 seconds and 12 minutes, respectively.
摘要翻译： 本发明公开了一种半导体器件的制造方法，该半导体器件在单元区域中形成高电压区域的厚栅极氧化膜和薄的隧道氧化物膜。 制造半导体器件的方法通过在高电压区域中生长约400埃的厚度的栅极氧化膜，从而缩短了处理时间并改善了高电压区域中的栅极氧化膜的均匀性，并且除去残留的氮化物膜 通过使用BOE溶液进行蚀刻处理和使用H 3 PO 4 S的蚀刻工艺分别在电池区域中进行120秒和12分钟。
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公开(公告)号：US20200013096A1
公开(公告)日：2020-01-09
申请号：US16029590
申请日：2018-07-07
申请人： Sang Park
发明人： Sang Park
摘要： A novel electronic system for third-party service portal-initiated garment service bag creation, distribution, volumetrically-standardized pricing, and matchmaking of professional garment cleaning is disclosed. The novel electronic system physically issues and electronically tracks volumetrically-standardized online garment service bags that are shipped to potential customers, who can then utilize such service bags to load garments at volumetrically-standardized fees per service bag and transport to a plurality of independent local garment cleaning service providers subscribed to the third-party service portal. The novel electronic system also enables the plurality of independent local garment cleaning service providers to define and competitively offer garment cleaning service fees that are objectively price-comparable on a price-per-unit bag metric of laundry load due to the volumetric standardization and the pre-distribution of online garment service bags by the third-party service portal, even before the potential customers utilize such service bags to load and ship garments to garment cleaning service providers.
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公开(公告)号：US07773402B2
公开(公告)日：2010-08-10
申请号：US12483482
申请日：2009-06-12
申请人： Sang Park , Shin Ho Chu
发明人： Sang Park , Shin Ho Chu
CPC分类号： G11C5/145 , H01L25/0657 , H01L2224/48225 , H01L2224/48227 , H01L2225/06568 , H01L2924/15311
摘要： A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.
摘要翻译： 响应于自刷新和有效信号，第一信号输入电路输出第一控制信号。 第二信号输入电路响应于自刷新和有效信号而输出第二控制信号。 电源电路响应于第一控制信号向输出端施加第一电源电压。 升高的电压发生器通过泵浦第二电源电压产生升高的电压，并且响应于第一和第二控制信号将升高的电压施加到输出端子。
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