公开(公告)号：US20080123386A1

公开(公告)日：2008-05-29

申请号：US11864604

申请日：2007-09-28

申请人： Sun-Won KANG ,  Seung-Duk BAEK

发明人： Sun-Won KANG ,  Seung-Duk BAEK

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.

摘要翻译： 提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。 半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。 第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。 一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。 第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

公开(公告)号：US20080116558A1

公开(公告)日：2008-05-22

申请号：US11935953

申请日：2007-11-06

申请人： Sun-Won KANG ,  Seung-Duk BAEK

发明人： Sun-Won KANG ,  Seung-Duk BAEK

IPC分类号： H01L23/02 ,  H01G4/06 ,  H01L21/02

CPC分类号： H01G4/06 ,  H01G4/1227 ,  H01G4/308 ,  H01L23/50 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A decoupling capacitor, a wafer stack package including the decoupling capacitor, and a method of fabricating the wafer stack package are provided. The decoupling capacitor may include a first electrode formed on an upper surface of a first wafer, a second electrode formed on a lower surface of a second wafer, and an adhesive material having a high dielectric constant and combining the first wafer with the second wafer. In the decoupling capacitor the first and second electrodes operate as two electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor.

摘要翻译： 提供去耦电容器，包括去耦电容器的晶片堆叠封装以及制造晶片堆叠封装的方法。 去耦电容器可以包括形成在第一晶片的上表面上的第一电极，形成在第二晶片的下表面上的第二电极和具有高介电常数并且将第一晶片与第二晶片组合的粘合材料。 在去耦电容器中，第一和第二电极作为去耦电容器的两个电极工作，并且粘合材料作为去耦电容器的电介质。

公开(公告)号：US20090001367A1

公开(公告)日：2009-01-01

申请号：US12116150

申请日：2008-05-06

申请人： Seung-Duk BAEK ,  Sun-Won KANG

发明人： Seung-Duk BAEK ,  Sun-Won KANG

IPC分类号： H01L23/482

CPC分类号： H01L23/5382 ,  H01L23/481 ,  H01L23/5258 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/4813 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device in which a plurality of chips can be reliably stacked without reducing integration thereof. The semiconductor device includes a substrate on which a circuit is provided. Pads are disposed on the substrate for testing the circuit. At least one terminal is provided on the substrate. First conductors are used to electrically couple the pads and the circuit. Second conductors are used to electrically couple the at least one terminal and the circuit. A switching element is disposed in the middle of the first conductors to control the electrical connection between the pads and the circuit. A plurality of semiconductor devices may be stacked on top of one another to form a stacked module, wherein chip selection lines are formed, which extend to the bottom of each of the semiconductor devices to electrically couple chip selection terminals from among the at least one terminal of the semiconductor devices.

摘要翻译： 可以可靠地层叠多个芯片而不降低其一体化的半导体装置。 半导体器件包括其上设置有电路的衬底。 垫片设置在基板上用于测试电路。 在基板上设置至少一个端子。 第一导体用于电连接焊盘和电路。 第二导体用于电耦合至少一个端子和电路。 开关元件设置在第一导体的中间，以控制焊盘和电路之间的电连接。 多个半导体器件可以堆叠在彼此的顶部以形成堆叠的模块，其中形成芯片选择线，其延伸到每个半导体器件的底部，以将芯片选择端子从至少一个端子 的半导体器件。

公开(公告)号：US20080128882A1

公开(公告)日：2008-06-05

申请号：US11949523

申请日：2007-12-03

申请人： Seung-Duk BAEK ,  Sun-Won KANG

发明人： Seung-Duk BAEK ,  Sun-Won KANG

IPC分类号： H01L23/02 ,  H01L21/02

CPC分类号： H01L25/18 ,  H01L21/568 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip stack package comprising an intermediate substrate having a recess, a first chip mounted in the recess, a second chip over the intermediate substrate, a package substrate formed under the intermediate substrate and first plugs through the intermediate substrate is disclosed. The second chip is configured to be electrically connected to the first chip. The first plugs are configured to electrically connect the second chip and the package substrate.

摘要翻译： 一种芯片堆叠封装，包括具有凹槽的中间衬底，安装在凹槽中的第一芯片，中间衬底上的第二芯片，形成在中间衬底之下的封装衬底，并且首先插入穿过中间衬底。 第二芯片被配置为电连接到第一芯片。 第一插头被配置为电连接第二芯片和封装基板。

公开(公告)号：US20110316159A1

公开(公告)日：2011-12-29

申请号：US13224670

申请日：2011-09-02

申请人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

发明人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US20090108469A1

公开(公告)日：2009-04-30

申请号：US12171035

申请日：2008-07-10

申请人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

发明人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US20080246113A1

公开(公告)日：2008-10-09

申请号：US12098352

申请日：2008-04-04

申请人： Seung-Duk BAEK ,  Sun-Won KANG ,  Hyun-Soo CHUNG

发明人： Seung-Duk BAEK ,  Sun-Won KANG ,  Hyun-Soo CHUNG

IPC分类号： H01L29/00

CPC分类号： H01L23/525 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L2224/02233 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00

摘要： The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案， 第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。 还提供了一种制造该方法的方法。

公开(公告)号：US20080304242A1

公开(公告)日：2008-12-11

申请号：US12126313

申请日：2008-05-23

申请人： Seung-Duk BAEK ,  Mitsuo UMEMOTO ,  Kang-Wook LEE

发明人： Seung-Duk BAEK ,  Mitsuo UMEMOTO ,  Kang-Wook LEE

IPC分类号： H05K7/00

CPC分类号： H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541

摘要： Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.

摘要翻译： 提供了通过使用简化的处理以低成本制造的高可靠性堆栈模块，使用堆栈模块的卡和使用堆栈模块的系统。 在堆叠模块中，单元基板相对于彼此层叠，并且每个单元基板包括选择端子。 第一选择线电连接到设置在奇数层的第一单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。 第二选择线电连接到以偶数层布置的第二单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。 选择端子设置在第一选择线和第二选择线之间。

公开(公告)号：US20080048322A1

公开(公告)日：2008-02-28

申请号：US11837577

申请日：2007-08-13

申请人： Seung-Duk BAEK ,  Dong-Hyeon JANG ,  Jong-Joo LEE

发明人： Seung-Duk BAEK ,  Dong-Hyeon JANG ,  Jong-Joo LEE

IPC分类号： H01L23/52

CPC分类号： H01L24/12 ,  H01L21/76807 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014

摘要： A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

摘要翻译： 半导体器件封装包括衬底，在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分，其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线，电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。