公开(公告)号：US20080246113A1

公开(公告)日：2008-10-09

申请号：US12098352

申请日：2008-04-04

申请人： Seung-Duk BAEK ,  Sun-Won KANG ,  Hyun-Soo CHUNG

发明人： Seung-Duk BAEK ,  Sun-Won KANG ,  Hyun-Soo CHUNG

IPC分类号： H01L29/00

CPC分类号： H01L23/525 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L2224/02233 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00

摘要： The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案， 第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。 还提供了一种制造该方法的方法。

公开(公告)号：US20090001367A1

公开(公告)日：2009-01-01

申请号：US12116150

申请日：2008-05-06

申请人： Seung-Duk BAEK ,  Sun-Won KANG

发明人： Seung-Duk BAEK ,  Sun-Won KANG

IPC分类号： H01L23/482

CPC分类号： H01L23/5382 ,  H01L23/481 ,  H01L23/5258 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/4813 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device in which a plurality of chips can be reliably stacked without reducing integration thereof. The semiconductor device includes a substrate on which a circuit is provided. Pads are disposed on the substrate for testing the circuit. At least one terminal is provided on the substrate. First conductors are used to electrically couple the pads and the circuit. Second conductors are used to electrically couple the at least one terminal and the circuit. A switching element is disposed in the middle of the first conductors to control the electrical connection between the pads and the circuit. A plurality of semiconductor devices may be stacked on top of one another to form a stacked module, wherein chip selection lines are formed, which extend to the bottom of each of the semiconductor devices to electrically couple chip selection terminals from among the at least one terminal of the semiconductor devices.

摘要翻译： 可以可靠地层叠多个芯片而不降低其一体化的半导体装置。 半导体器件包括其上设置有电路的衬底。 垫片设置在基板上用于测试电路。 在基板上设置至少一个端子。 第一导体用于电连接焊盘和电路。 第二导体用于电耦合至少一个端子和电路。 开关元件设置在第一导体的中间，以控制焊盘和电路之间的电连接。 多个半导体器件可以堆叠在彼此的顶部以形成堆叠的模块，其中形成芯片选择线，其延伸到每个半导体器件的底部，以将芯片选择端子从至少一个端子 的半导体器件。

公开(公告)号：US20080123386A1

公开(公告)日：2008-05-29

申请号：US11864604

申请日：2007-09-28

申请人： Sun-Won KANG ,  Seung-Duk BAEK

发明人： Sun-Won KANG ,  Seung-Duk BAEK

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.

摘要翻译： 提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。 半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。 第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。 一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。 第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

公开(公告)号：US20080116558A1

公开(公告)日：2008-05-22

申请号：US11935953

申请日：2007-11-06

申请人： Sun-Won KANG ,  Seung-Duk BAEK

发明人： Sun-Won KANG ,  Seung-Duk BAEK

IPC分类号： H01L23/02 ,  H01G4/06 ,  H01L21/02

CPC分类号： H01G4/06 ,  H01G4/1227 ,  H01G4/308 ,  H01L23/50 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A decoupling capacitor, a wafer stack package including the decoupling capacitor, and a method of fabricating the wafer stack package are provided. The decoupling capacitor may include a first electrode formed on an upper surface of a first wafer, a second electrode formed on a lower surface of a second wafer, and an adhesive material having a high dielectric constant and combining the first wafer with the second wafer. In the decoupling capacitor the first and second electrodes operate as two electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor.

摘要翻译： 提供去耦电容器，包括去耦电容器的晶片堆叠封装以及制造晶片堆叠封装的方法。 去耦电容器可以包括形成在第一晶片的上表面上的第一电极，形成在第二晶片的下表面上的第二电极和具有高介电常数并且将第一晶片与第二晶片组合的粘合材料。 在去耦电容器中，第一和第二电极作为去耦电容器的两个电极工作，并且粘合材料作为去耦电容器的电介质。

公开(公告)号：US20080128882A1

公开(公告)日：2008-06-05

申请号：US11949523

申请日：2007-12-03

申请人： Seung-Duk BAEK ,  Sun-Won KANG

发明人： Seung-Duk BAEK ,  Sun-Won KANG

IPC分类号： H01L23/02 ,  H01L21/02

CPC分类号： H01L25/18 ,  H01L21/568 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip stack package comprising an intermediate substrate having a recess, a first chip mounted in the recess, a second chip over the intermediate substrate, a package substrate formed under the intermediate substrate and first plugs through the intermediate substrate is disclosed. The second chip is configured to be electrically connected to the first chip. The first plugs are configured to electrically connect the second chip and the package substrate.

摘要翻译： 一种芯片堆叠封装，包括具有凹槽的中间衬底，安装在凹槽中的第一芯片，中间衬底上的第二芯片，形成在中间衬底之下的封装衬底，并且首先插入穿过中间衬底。 第二芯片被配置为电连接到第一芯片。 第一插头被配置为电连接第二芯片和封装基板。

公开(公告)号：US20110316159A1

公开(公告)日：2011-12-29

申请号：US13224670

申请日：2011-09-02

申请人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

发明人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US20090166840A1

公开(公告)日：2009-07-02

申请号：US12342689

申请日：2008-12-23

申请人： Sun-Won KANG ,  Seung-Duk Baek

发明人： Sun-Won KANG ,  Seung-Duk Baek

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.

摘要翻译： 晶圆级堆叠封装包括半导体芯片，第一连接构件，第二连接构件，基板和外部连接端子。 半导体芯片具有电源/接地焊盘和信号焊盘。 第一连接构件电连接到电源/接地焊盘和每个半导体芯片的信号焊盘。 第二连接构件电连接到每个半导体芯片的功率/接地焊盘中的至少一个，电源/接地焊盘连接到第一连接构件。 基板支撑层叠的半导体芯片，基板包括电连接到第一连接构件和第二连接构件的布线。 外部连接端子设置在与半导体芯片堆叠的表面相对的表面上，其中外部连接端子分别电连接到布线。

公开(公告)号：US20090108469A1

公开(公告)日：2009-04-30

申请号：US12171035

申请日：2008-07-10

申请人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

发明人： Sun-Won KANG ,  Seung-Duk BAEK ,  Jong-Joo LEE

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US20080290492A1

公开(公告)日：2008-11-27

申请号：US12123367

申请日：2008-05-19

申请人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Nam-Seog KIM ,  Sun-Won KANG

发明人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Nam-Seog KIM ,  Sun-Won KANG

IPC分类号： H01L23/488

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

摘要： Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad.

摘要翻译： 提供了具有增强的接头可靠性的半导体封装以及其制造方法。 该方法包括：形成包括插入在底层和顶层之间的半导体芯片的封装单元; 并且将所述封装单元依次堆叠在基板上。 底层和顶层由具有比半导体芯片低的模量的材料形成。 所述半导体封装包括：设置在基板上的至少一个封装单元，所述封装单元包括具有衬垫，底层和基本上围绕所述半导体芯片的顶层的半导体芯片以及覆盖所述顶层的再分布结构。 再分配结构电连接到焊盘。

公开(公告)号：US20070252271A1

公开(公告)日：2007-11-01

申请号：US11740821

申请日：2007-04-26

申请人： Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

发明人： Joong-Hyun BAEK ,  Sun-Won KANG ,  Moon-Jung KIM ,  Hyung-Gil BAEK ,  Hee-Jin LEE

IPC分类号： H01L23/34

CPC分类号： H01L25/16 ,  G11C5/04 ,  H01L21/563 ,  H01L25/0655 ,  H01L2224/73203 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10159 ,  Y02P70/611

摘要： Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

摘要翻译： 提供了一种半导体存储器模块，其允许形成在模块基板和安装在模块基板上的存储芯片之间的填充构件完全填充模块基板和存储器芯片之间的空间。 根据本发明的实施例，半导体存储器模块包括具有安装在基板上的至少一个存储芯片的模块基板，使得其边缘对于将模块基板平分的主轴和短轴倾斜。 倾斜方向允许在基板上形成的存储芯片之间的开口改善，使得填充构件可以适当地形成在模块基板和存储芯片之间，以防止填充构件未形成的空隙。