公开(公告)号：US20060138648A1

公开(公告)日：2006-06-29

申请号：US11305282

申请日：2005-12-16

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC分类号： H01L23/34

CPC分类号： H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

摘要翻译： 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。

公开(公告)号：US07652383B2

公开(公告)日：2010-01-26

申请号：US11305282

申请日：2005-12-16

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC分类号： H01L23/29

CPC分类号： H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

摘要翻译： 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。

公开(公告)号：US07586182B2

公开(公告)日：2009-09-08

申请号：US11289665

申请日：2005-11-28

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

摘要翻译： 本文描述的主题的方面涉及成为成品多芯片封装的部件的封装半导体管芯。 封装的半导体管芯包括管芯衬底，半导体封装和密封剂。 芯片基板包括绝缘基板和形成在绝缘基板上的电路图案。 半导体封装具有电耦合到电路图案的半导体芯片，该电路图案是已知的良好封装并且耦合到管芯衬底。 密封剂密封半导体封装。 封装的半导体管芯使用已经通过一系列封装测试的已知的良好封装。

公开(公告)号：US20060134833A1

公开(公告)日：2006-06-22

申请号：US11289665

申请日：2005-11-28

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC分类号： H01L21/48

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

公开(公告)号：US20100090326A1

公开(公告)日：2010-04-15

申请号：US12588382

申请日：2009-10-14

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.

摘要翻译： 堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。 第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。 第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。 电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口电连接到第一半导体芯片的通孔，与焊盘间隔开的外连接焊盘和 连接配线，从连接焊盘的开口延伸到外部连接焊盘。

公开(公告)号：US08097940B2

公开(公告)日：2012-01-17

申请号：US12588382

申请日：2009-10-14

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.

摘要翻译： 堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。 第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。 第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。 电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口与第一半导体芯片的通孔电连接，与焊盘间隔开的外连接焊盘和 连接配线，从连接焊盘的开口延伸到外部连接焊盘。

公开(公告)号：US08446016B2

公开(公告)日：2013-05-21

申请号：US13224670

申请日：2011-09-02

申请人： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

发明人： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US08039928B2

公开(公告)日：2011-10-18

申请号：US12171035

申请日：2008-07-10

申请人： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

发明人： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

摘要翻译： 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US08143693B2

公开(公告)日：2012-03-27

申请号：US12098352

申请日：2008-04-04

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Hyun-Soo Chung

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Hyun-Soo Chung

IPC分类号： H01L29/00

CPC分类号： H01L23/525 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L2224/02233 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00

摘要： The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案， 第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。 还提供了一种制造该方法的方法。

公开(公告)号：US20100102434A1

公开(公告)日：2010-04-29

申请号：US12652875

申请日：2010-01-06

申请人： Sun-Won Kang ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Seung-Duk Baek

IPC分类号： H01L25/16 ,  H01L23/498

CPC分类号： G11C5/063 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.

摘要翻译： 提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。 半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。 第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。 一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。 第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。