公开(公告)号：US20060138648A1

公开(公告)日：2006-06-29

申请号：US11305282

申请日：2005-12-16

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC分类号： H01L23/34

CPC分类号： H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

摘要翻译： 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。

公开(公告)号：US20060134833A1

公开(公告)日：2006-06-22

申请号：US11289665

申请日：2005-11-28

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC分类号： H01L21/48

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

公开(公告)号：US07652383B2

公开(公告)日：2010-01-26

申请号：US11305282

申请日：2005-12-16

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Dong-Ho Lee ,  Jong-Joo Lee ,  Sang-Wook Park

IPC分类号： H01L23/29

CPC分类号： H01L25/105 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K2201/10477 ,  H05K2201/10977 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

摘要翻译： 提供一种不具有焊球的半导体封装模块和制造该半导体封装模块的方法。 该半导体封装模块包括：模块板，多个半导体器件能够安装在该模块板上;半导体封装，使用粘合剂结合在模块板上，可与模块板接合，并且已经经过电气最终测试 ，将所述半导体封装的第二接合焊盘与所述模块板的焊盘电连接的第二布线; 以及封装第二导线和半导体封装的第三密封树脂。 由于半导体封装模块不使用焊球，因此可以防止焊点可靠性（SJR）的劣化。 此外，使用已经经历电测试的半导体封装可以降低完成的半导体封装模块的产量的劣化。

公开(公告)号：US07586182B2

公开(公告)日：2009-09-08

申请号：US11289665

申请日：2005-11-28

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

摘要翻译： 本文描述的主题的方面涉及成为成品多芯片封装的部件的封装半导体管芯。 封装的半导体管芯包括管芯衬底，半导体封装和密封剂。 芯片基板包括绝缘基板和形成在绝缘基板上的电路图案。 半导体封装具有电耦合到电路图案的半导体芯片，该电路图案是已知的良好封装并且耦合到管芯衬底。 密封剂密封半导体封装。 封装的半导体管芯使用已经通过一系列封装测试的已知的良好封装。

公开(公告)号：US07301233B2

公开(公告)日：2007-11-27

申请号：US11169615

申请日：2005-06-30

申请人： Hae-Hyung Lee ,  Sang-Wook Park ,  Joong-Hyun Baek ,  Dong-Ho Lee ,  Jin-Yang Lee

发明人： Hae-Hyung Lee ,  Sang-Wook Park ,  Joong-Hyun Baek ,  Dong-Ho Lee ,  Jin-Yang Lee

IPC分类号： H01L23/34 ,  H01L23/10 ,  H01L23/02

CPC分类号： H01L23/38 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/37599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The semiconductor chip package may include a substrate having circuit patterns and substrate pads connected with the circuit patterns. At least one semiconductor chip is mounted on the substrate, and a thermoelectric cooler having a P-type material plate and an N-type material plate is mounted on the semiconductor chip. Portions of the P-type and N-type material plates may be attached on the semiconductor chip. The P-type and N-type material plates may be electrically connected to the circuit patterns of the substrate to be provided with DC power.

摘要翻译： 半导体芯片封装可以包括具有电路图案的衬底和与电路图案连接的衬底焊盘。 至少一个半导体芯片安装在基板上，并且具有P型材料板和N型材料板的热电冷却器安装在半导体芯片上。 P型和N型材料板的部分可以附着在半导体芯片上。 P型和N型材料板可以电连接到衬底的电路图案以提供DC电力。

公开(公告)号：US20060006517A1

公开(公告)日：2006-01-12

申请号：US11176800

申请日：2005-07-06

申请人： Jin-Yang Lee ,  Sang-Wook Park ,  Hae-Hyung Lee ,  Dong-Ho Lee ,  Joong-Hyun Baek

发明人： Jin-Yang Lee ,  Sang-Wook Park ,  Hae-Hyung Lee ,  Dong-Ho Lee ,  Joong-Hyun Baek

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A multi-chip package having a heat dissipating path. The multi-chip package includes a stack of integrated circuit (IC) chips, a heat sink part interposed between the IC chips so that one end portion of the heat sink part can be exposed from a side of the stack of integrated circuit chips, a substrate on which the stack of integrated circuit chips is mounted, and solder or solder ball-shaped thermally connecting parts to thermally connect the exposed end portion of the heat sink part to the substrate to dissipate heat collected in the heat sink part through the substrate.

摘要翻译： 具有散热路径的多芯片封装。 多芯片封装包括集成电路（IC）芯片堆叠，插入在IC芯片之间的散热器部分，使得散热部件的一个端部可以从集成电路芯片堆叠的一侧露出， 其上安装有集成电路芯片的堆叠的基板，以及焊料或焊球形的热连接部件，以将散热部件的暴露端部热连接到基板，以散发通过基板收集在散热部件中的热量。

公开(公告)号：US20060001140A1

公开(公告)日：2006-01-05

申请号：US11169615

申请日：2005-06-30

申请人： Hae-Hyung Lee ,  Sang-Wook Park ,  Joong-Hyun Baek ,  Dong-Ho Lee ,  Jin-Yang Lee

发明人： Hae-Hyung Lee ,  Sang-Wook Park ,  Joong-Hyun Baek ,  Dong-Ho Lee ,  Jin-Yang Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/38 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/37599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The semiconductor chip package may include a substrate having circuit patterns and substrate pads connected with the circuit patterns. At least one semiconductor chip is mounted on the substrate, and a thermoelectric cooler having a P-type material plate and an N-type material plate is mounted on the semiconductor chip. Portions of the P-type and N-type material plates may be attached on the semiconductor chip. The P-type and N-type material plates may be electrically connected to the circuit patterns of the substrate to be provided with DC power.

摘要翻译： 半导体芯片封装可以包括具有电路图案的衬底和与电路图案连接的衬底焊盘。 至少一个半导体芯片安装在基板上，并且具有P型材料板和N型材料板的热电冷却器安装在半导体芯片上。 P型和N型材料板的部分可以附着在半导体芯片上。 P型和N型材料板可以电连接到衬底的电路图案以提供DC电力。

公开(公告)号：US08552546B2

公开(公告)日：2013-10-08

申请号：US12896091

申请日：2010-10-01

申请人： In-Sang Song ,  Seok-Keun Lim ,  In-Wook Jung ,  Bong-Ken Yu ,  Sang-Wook Park ,  Ji-Seok Hong

发明人： In-Sang Song ,  Seok-Keun Lim ,  In-Wook Jung ,  Bong-Ken Yu ,  Sang-Wook Park ,  Ji-Seok Hong

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/078 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： Provided is a semiconductor package. The semiconductor package may include a first semiconductor package having first semiconductor chips sequentially stacked on a substrate. In example embodiments, the first semiconductor chips may have a cascaded arrangement in which first sides and second sides of the semiconductor chips define cascade patterns. The cascaded arrangement may extend in a first direction to define a space between the first sides of the first semiconductor chips and the substrate. The semiconductor package may also include at least one first connection wiring at the second sides of the semiconductor chips, the at least one first connection wiring being configured to electrically connect the substrate with the first semiconductor chips. In addition, the semiconductor package may further include a first filling auxiliary structure adjacent to the first sides of the first semiconductor chips.

摘要翻译： 提供半导体封装。 半导体封装可以包括具有顺序地堆叠在衬底上的第一半导体芯片的第一半导体封装。 在示例性实施例中，第一半导体芯片可以具有级联布置，其中半导体芯片的第一侧和第二侧限定级联图案。 级联布置可以在第一方向上延伸以限定第一半导体芯片的第一侧和基板之间的空间。 半导体封装还可以包括在半导体芯片的第二面处的至少一个第一连接布线，所述至少一个第一连接布线被配置为将衬底与第一半导体芯片电连接。 此外，半导体封装还可以包括与第一半导体芯片的第一侧相邻的第一填充辅助结构。

公开(公告)号：US08317056B2

公开(公告)日：2012-11-27

申请号：US11777155

申请日：2007-07-12

申请人： Dai-Gil Lee ,  Sang-Wook Park ,  Byung-Chul Kim ,  Seong-su Kim

发明人： Dai-Gil Lee ,  Sang-Wook Park ,  Byung-Chul Kim ,  Seong-su Kim

IPC分类号： F17C1/06 ,  F17C1/00 ,  F17C3/00 ,  F17C13/00

CPC分类号： F17C13/001 ,  F17C2203/0304 ,  F17C2203/0329 ,  F17C2203/0345 ,  F17C2203/035 ,  F17C2203/0358 ,  F17C2203/0643 ,  F17C2209/227 ,  F17C2221/033 ,  F17C2260/011 ,  F17C2270/01 ,  Y10T29/49616

摘要： A structure and method for bonding heat-insulating protection walls of a liquefied natural gas carrier is provided. Each of the heat-insulating protection walls is formed of an insulation foam layer and a fiber-reinforced composite reinforcing sheet attached to a surface of the insulation foam layer. The heat-insulating protection walls are provided in a tank of the liquefied natural gas carrier in a mutually adjoining relationship and bonded to one another at a junction to keep the tank cold. The structure includes a fiber-reinforced composite joint sheet positioned in alignment with the juncture of the heat-insulating protection walls and bonded to the fiber-reinforced composite reinforcing sheet by an adhesive agent and a spacer interposed between the fiber-reinforced composite reinforcing sheet and the fiber-reinforced composite joint sheet for keeping the adhesive agent uniform in thickness.

摘要翻译： 提供了一种用于粘合液化天然气载体的隔热保护壁的结构和方法。 每个绝热保护壁由绝缘泡沫层和附着在绝缘泡沫层的表面上的纤维增强复合增强片形成。 隔热保护壁以相互邻接的关系设置在液化天然气载体的槽中，并且在连接处彼此粘合以保持冷藏。 该结构包括与隔热保护壁的接合部对准的纤维增强复合接合片，并通过粘合剂与间隔开的纤维增强复合增强片粘贴，纤维增强复合增强片与纤维增强复合增强片 用于保持粘合剂厚度均匀的纤维增强复合接合片。

公开(公告)号：US08022517B2

公开(公告)日：2011-09-20

申请号：US12266765

申请日：2008-11-07

申请人： Sung-Hwan Yoon ,  Sang-Wook Park ,  Min-Young Son

发明人： Sung-Hwan Yoon ,  Sang-Wook Park ,  Min-Young Son

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/293 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring.

摘要翻译： 半导体芯片封装包括引线框架，绝缘构件，芯片，接合线和密封构件。 引线框架包括多个第一引线和多个第二引线。 第二引线具有芯片粘附区域。 绝缘构件填充芯片粘合区域中的第二引线之间的空间。 芯片设置在绝缘构件的至少一个表面上。 该芯片具有单面接合焊盘。 接合线将引线和接合焊盘电连接。 密封构件覆盖引线框架，绝缘构件，芯片和接合线。 由于第二引线之间的空间填充有绝缘构件，因此可以防止发生空隙。