公开(公告)号：US20090050974A1

公开(公告)日：2009-02-26

申请号：US12244573

申请日：2008-10-02

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L47/00 ,  H01L21/8234

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US07473943B2

公开(公告)日：2009-01-06

申请号：US11233398

申请日：2005-09-22

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L29/80

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US20100144103A1

公开(公告)日：2010-06-10

申请号：US12703043

申请日：2010-02-09

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L21/8232 ,  H01L21/302

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US20100167512A1

公开(公告)日：2010-07-01

申请号：US12720125

申请日：2010-03-09

申请人： Yaoling Pan ,  Jian Chen ,  Francisco Leon ,  Shahriar Mostarshed ,  Linda T. Romano ,  Vijendra Sahi ,  David P. Stumbo

发明人： Yaoling Pan ,  Jian Chen ,  Francisco Leon ,  Shahriar Mostarshed ,  Linda T. Romano ,  Vijendra Sahi ,  David P. Stumbo

IPC分类号： H01L21/22

CPC分类号： H01L29/0665 ,  B81C1/00698 ,  B81C2201/0173 ,  B82Y10/00 ,  H01L21/2256 ,  H01L21/268 ,  H01L29/0673

摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

摘要翻译： 公开了掺杂纳米结构的方法，例如纳米线。 该方法提供了改进现有掺杂纳米结构方法的各种方法。 这些实施方案包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。 在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。 在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。 在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。 还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料以在所得纳米结构内实现新的晶体结构。

公开(公告)号：US07701014B2

公开(公告)日：2010-04-20

申请号：US12244573

申请日：2008-10-02

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L27/088

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US20060081886A1

公开(公告)日：2006-04-20

申请号：US11233398

申请日：2005-09-22

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda Romano

IPC分类号： H01L29/76

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US07345307B2

公开(公告)日：2008-03-18

申请号：US11233503

申请日：2005-09-22

申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

IPC分类号： H01L29/10

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

公开(公告)号：US20060214156A1

公开(公告)日：2006-09-28

申请号：US11233503

申请日：2005-09-22

申请人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

发明人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

IPC分类号： H01L29/08

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

公开(公告)号：US20080128688A1

公开(公告)日：2008-06-05

申请号：US12016701

申请日：2008-01-18

申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

IPC分类号： H01L51/05

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

公开(公告)号：US20080150003A1

公开(公告)日：2008-06-26

申请号：US11641956

申请日：2006-12-20

申请人： Jian Chen ,  Xiangfeng Duan ,  Karen Cruden ,  Chao Liu ,  Madhuri L. Nallabolu ,  Srikanth Ranganathan ,  Francisco Leon ,  J. Wallace Parce

发明人： Jian Chen ,  Xiangfeng Duan ,  Karen Cruden ,  Chao Liu ,  Madhuri L. Nallabolu ,  Srikanth Ranganathan ,  Francisco Leon ,  J. Wallace Parce

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/517

摘要： Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

摘要翻译： 描述诸如非易失性存储器件的电子设备的方法和装置。 存储器件包括多层控制电介质，例如双层或三层。 多层控制电介质包括高k电介质材料如氧化铝（Al 2 O 3），氧化铪（HfO 2）和/或铪铝氧化物的混合膜的组合。 多层控制电介质提供增强的特性，包括增加的电荷保留，增强的存储器编程/擦除窗口，改进的可靠性和稳定性，具有单或多（例如二，三或四位）操作的可行性。