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    Large area nanoenabled macroelectronic substrates and uses therefor
    1.
    发明授权
    Large area nanoenabled macroelectronic substrates and uses therefor 有权
    大面积纳米大电子基板及其用途

    公开(公告)号：US08293624B2

    公开(公告)日：2012-10-23

    申请号：US13218286

    申请日：2011-08-25

    Applicant: Linda T. Romano ,  Jian Chen

    Inventor： Linda T. Romano ,  Jian Chen

    IPC: H01L21/20 ,  H01L21/36

    CPC classification number: H01L29/78696 ,  B82Y10/00 ,  B82Y25/00 ,  H01F1/0072 ,  H01L27/1214 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L33/08 ,  H01L33/18 ,  H01L35/26 ,  H01L35/32 ,  H01L41/082 ,  H01L41/18 ,  H01L41/316 ,  H01L51/0012 ,  H01L51/0048 ,  H01L51/0504 ,  H01L51/0508 ,  H01L51/0545 ,  H01L51/0595 ,  Y02E10/549

    Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

    Abstract translation: 描述了具有多个半导体器件的电子基片的方法和装置。 在衬底上形成纳米线薄膜。 纳米线的薄膜形成为具有足够的纳米线密度以达到工作电流水平。 在纳米线的薄膜中限定多个半导体区域。 在半导体器件区域处形成触点，从而提供与多个半导体器件的电连接。 此外，用于制造纳米线的各种材料，包括p掺杂纳米线和n掺杂纳米线的薄膜，纳米线异质结构，发光纳米线异质结构，用于在衬底上定位纳米线的流动掩模，用于沉积纳米线的纳米线喷涂技术，用于减少或消除声子的技术 描述了纳米线中的电子散射，以及用于降低纳米线中的表面状态的技术。

    Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices
    7.
    发明申请
    Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices 有权
    基于纳米线的电子设备中门控配置和改进接点的方法，系统和设备

    公开(公告)号：US20100144103A1

    公开(公告)日：2010-06-10

    申请号：US12703043

    申请日：2010-02-09

    Applicant: Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    Inventor： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC: H01L21/8232 ,  H01L21/302

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    Abstract translation: 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    III-nitride light emitting device with reduced strain light emitting layer
    8.
    发明授权
    III-nitride light emitting device with reduced strain light emitting layer 有权
    具有减小的应变发光层的III族氮化物发光器件

    公开(公告)号：US07663148B2

    公开(公告)日：2010-02-16

    申请号：US11615479

    申请日：2006-12-22

    Applicant: Sungsoo Yi ,  Aurelien J. F. David ,  Nathan F. Gardner ,  Michael R. Krames ,  Linda T. Romano

    Inventor： Sungsoo Yi ,  Aurelien J. F. David ,  Nathan F. Gardner ,  Michael R. Krames ,  Linda T. Romano

    IPC: H01L33/00

    CPC classification number: H01L33/007 ,  H01L33/12 ,  H01L33/22

    Abstract: In accordance with embodiments of the invention, strain is reduced in the light emitting layer of a III-nitride device by including a strain-relieved layer in the device. The surface on which the strain-relieved layer is grown is configured such that strain-relieved layer can expand laterally and at least partially relax. In some embodiments of the invention, the strain-relieved layer is grown over a textured semiconductor layer or a mask layer. In some embodiments of the invention, the strain-relieved layer is group of posts of semiconductor material.

    Abstract translation: 根据本发明的实施例，通过在器件中包括应变消除层，在III族氮化物器件的发光层中应变被减小。 应变消除层生长在其上的表面被配置成使得应变消除层可以横向膨胀并且至少部分地松弛。 在本发明的一些实施方案中，应变释放层在织构化的半导体层或掩模层上生长。 在本发明的一些实施例中，应变消除层是半导体材料的一组柱。

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