公开(公告)号：US08653559B2

公开(公告)日：2014-02-18

申请号：US13171798

申请日：2011-06-29

申请人： Andrea Corrion ,  Karim S. Boutros ,  Mary Y. Chen ,  Samuel J. Kim ,  Rongming Chu ,  Shawn D. Burnham

发明人： Andrea Corrion ,  Karim S. Boutros ,  Mary Y. Chen ,  Samuel J. Kim ,  Rongming Chu ,  Shawn D. Burnham

IPC分类号： H01L29/66 ,  H01L21/338

CPC分类号： H01L29/4236 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.

摘要翻译： 场效应晶体管（FET）包括源极和漏极，沟道层，沟道层上的势垒层，覆盖阻挡层以钝化势垒层的钝化层，延伸穿过阻挡层的栅电极和钝化层 以及围绕所述栅电极的延伸穿过所述阻挡层和所述钝化层的部分的栅极电介质，其中所述钝化层是第一材料，并且所述栅极电介质是第二材料，并且所述第一材料不同于所述第二材料 。

公开(公告)号：US20130001646A1

公开(公告)日：2013-01-03

申请号：US13171798

申请日：2011-06-29

申请人： Andrea Corrion ,  Karim S. Boutros ,  Mary Y. Chen ,  Samuel J. Kim ,  Rongming Chu ,  Shawn D. Burnham

发明人： Andrea Corrion ,  Karim S. Boutros ,  Mary Y. Chen ,  Samuel J. Kim ,  Rongming Chu ,  Shawn D. Burnham

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/4236 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

摘要： A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.

摘要翻译： 场效应晶体管（FET）包括源极和漏极，沟道层，沟道层上的势垒层，覆盖阻挡层以钝化势垒层的钝化层，延伸穿过阻挡层的栅电极和钝化层 以及围绕所述栅电极的延伸穿过所述阻挡层和所述钝化层的部分的栅极电介质，其中所述钝化层是第一材料，并且所述栅极电介质是第二材料，并且所述第一材料不同于所述第二材料 。

公开(公告)号：US08124505B1

公开(公告)日：2012-02-28

申请号：US12909497

申请日：2010-10-21

申请人： Shawn D Burnham ,  Karim S. Boutros

发明人： Shawn D Burnham ,  Karim S. Boutros

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L31/20

CPC分类号： H01L21/30621 ,  H01L21/02241 ,  H01L29/66462

摘要： A two stage plasma etching technique is described that allows the fabrication of an enhancement mode GaN HFET/HEMT. A gate recess area is formed in the Aluminum Gallium Nitride barrier layer of an GaN HFET/HEMT. The gate recess is formed by a two stage etching process. The first stage of the technique uses oxygen to oxidize the surface of the Aluminum Gallium Nitride barrier layer below the gate. Then the second stage uses Boron tricloride to remove the oxidized layer. The result is a self limiting etch process that uniformly thins the Aluminum Gallium Nitride layer below the HFET's gate region such that the two dimensional electron gas is not formed below the gate, thus creating an enhancement mode HFET.

摘要翻译： 描述了允许制造增强型GaN HFET / HEMT的两级等离子体蚀刻技术。 在GaN HFET / HEMT的氮化镓氮化镓阻挡层中形成栅极凹部。 门槽通过两级蚀刻工艺形成。 该技术的第一阶段使用氧来氧化栅极下方的氮化镓镓屏障层的表面。 然后第二阶段使用三氯化硼去除氧化层。 结果是自限蚀刻工艺，其均匀地使HFET栅极区域下方的氮化镓镓层均匀地沉淀，使得二维电子气体不形成在栅极下方，从而产生增强模式HFET。

公开(公告)号：US20130328061A1

公开(公告)日：2013-12-12

申请号：US13604983

申请日：2012-09-06

申请人： Rongming Chu ,  Brian Hughes ,  Andrea Corrion ,  Shawn D. Burnham ,  Karim S. Boutros

发明人： Rongming Chu ,  Brian Hughes ,  Andrea Corrion ,  Shawn D. Burnham ,  Karim S. Boutros

IPC分类号： H01L29/778 ,  H01L29/24 ,  H01L21/335 ,  H01L29/20

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/7787

摘要： A normally-off transistor includes a channel layer, an electron supply layer overlaying the channel layer, a source electrode and a drain electrode on the electron supply layer, an area in the electrode supply layer between the source electrode and the drain electrode treated with a fluoride based plasma followed by a chlorine based plasma treatment, a gate insulator overlaying the area, and a gate electrode overlaying the gate insulator.

摘要翻译： 常闭晶体管包括沟道层，覆盖沟道层的电子供应层，电子供应层上的源极和漏电极，源电极和漏电极之间的电极供应层中的区域 氟化物基等离子体，然后进行氯基等离子体处理，覆盖该区域的栅极绝缘体和覆盖栅极绝缘体的栅电极。

公开(公告)号：US09379195B2

公开(公告)日：2016-06-28

申请号：US13478609

申请日：2012-05-23

申请人： Sameh G. Khalil ,  Karim S. Boutros ,  Keisuke Shinohara

发明人： Sameh G. Khalil ,  Karim S. Boutros ,  Keisuke Shinohara

IPC分类号： H01L21/336 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/4236 ,  H01L29/06 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain. A two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain.

摘要翻译： 具有衬底，衬底上的沟道层和沟道层上的阻挡层的高电子迁移率场效应晶体管（HEMT）包括在阻挡层上的应力诱导层，应力诱导层改变了压电效应 栅极和漏极之间的漂移区域中的阻挡层。 二维电子气（2DEG）在栅极和漏极之间的漂移区域中具有不均匀的横向分布。

公开(公告)号：US20130026495A1

公开(公告)日：2013-01-31

申请号：US13456039

申请日：2012-04-25

申请人： Rongming Chu ,  David F. Brown ,  Xu Chen ,  Adam J. Williams ,  Karim S. Boutros

发明人： Rongming Chu ,  David F. Brown ,  Xu Chen ,  Adam J. Williams ,  Karim S. Boutros

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/205

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/2006 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78

摘要： A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

摘要翻译： 场效应晶体管（FET）包括III-氮化物沟道层，沟道层上的III-氮化物阻挡层，其中该阻挡层具有比该沟道层大的能带隙，该电极与III 氮化物层，电耦合到III族氮化物层之一的漏电极，用于将栅极电极与阻挡层电绝缘的栅极绝缘体层堆叠和沟道层，栅极绝缘体层堆叠包括绝缘体层，例如 SiN和AlN层，栅极电极在源电极和漏电极之间的区域中并与绝缘体层接触，并且其中AlN层与III-氮化物层之一接触。

公开(公告)号：US07893791B2

公开(公告)日：2011-02-22

申请号：US12256321

申请日：2008-10-22

申请人： Yin Tat Ma ,  Jonathan Hacker ,  Karim S. Boutros

发明人： Yin Tat Ma ,  Jonathan Hacker ,  Karim S. Boutros

IPC分类号： H01P1/10 ,  H01P5/12

CPC分类号： H01P1/15

摘要： Devices and systems for using a Gallium Nitride-based (GaN-based) transistor for selectively switching signals are provided. A first transmission line is configured to connect a common connection and a first connection. A first Gallium-Nitride-based (GaN-based) transistor has a first terminal coupled to the first transmission line at a first point, a second terminal coupled to a relative ground, and a third terminal configured to be coupled to a first control connection. A second GaN-based transistor has a first terminal coupled to the first transmission line at a second point, a second terminal configured to be coupled to the relative ground, and a third terminal configured to be coupled to the first control connection.

摘要翻译： 提供了用于选择性地切换信号的使用基于氮化镓（GaN）的晶体管的器件和系统。 第一传输线被配置为连接公共连接和第一连接。 第一基于氮化镓的（GaN基）晶体管具有在第一点处耦合到第一传输线的第一端子，耦合到相对地的第二端子，以及被配置为耦合到第一控制连接 。 第二GaN基晶体管具有在第二点处耦合到第一传输线的第一端子，被配置为耦合到相对地的第二端子，以及被配置为耦合到第一控制连接的第三端子。

公开(公告)号：US09368622B1

公开(公告)日：2016-06-14

申请号：US13109223

申请日：2011-05-17

申请人： Karim S. Boutros

发明人： Karim S. Boutros

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/778

CPC分类号： H01L29/7831 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66484 ,  H01L29/778 ,  H01L29/7786

摘要： Principles of the present invention reduces the maximum electric field strength between a gate and a source or drain in a FET by breaking up the usually monolithic gate into a plurality of physically separate subgates that are electrically connected into one or more groups.

摘要翻译： 本发明的原理通过将通常的单片栅极分解成电连接到一个或多个组中的多个物理上分离的底座来减小FET中的栅极和源极或漏极之间的最大电场强度。

公开(公告)号：US08680536B2

公开(公告)日：2014-03-25

申请号：US13479018

申请日：2012-05-23

申请人： Sameh G. Khalil ,  Karim S. Boutros

发明人： Sameh G. Khalil ,  Karim S. Boutros

IPC分类号： H01L29/20

CPC分类号： H01L29/66431 ,  H01L21/0271 ,  H01L21/0275 ,  H01L21/3085 ,  H01L29/0843 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66469 ,  H01L29/772 ,  H01L29/7787

摘要： A HEMT device has a substrate; a buffer layer disposed above the substrate; a carrier supplying layer disposed above the buffer layer; a gate element penetrating the carrier supplying layer; and a drain element disposed on the carrier supplying layer. The carrier supplying layer has a non-uniform thickness between the gate element and the drain element, the carrier supplying layer having a relatively greater thickness adjacent the drain element and a relatively thinner thickness adjacent the gate element. A non-uniform two-dimensional electron gas conduction channel is formed in the carrier supplying layer, the two-dimensional electron gas conduction channel having a non-uniform profile between the gate and drain elements.

摘要翻译： HEMT装置具有基板; 设置在所述基板上方的缓冲层; 设置在所述缓冲层上方的载体供给层; 穿过载体供应层的栅极元件; 以及设置在载体供给层上的漏极元件。 载体供给层在栅极元件和漏极元件之间具有不均匀的厚度，载体供给层具有与漏极元件相邻的相对较大的厚度，并且邻近栅极元件具有相对较薄的厚度。 在载体供应层中形成不均匀的二维电子气导电通道，二维电子气传导通道在栅极和漏极之间具有不均匀的轮廓。

公开(公告)号：US07151307B2

公开(公告)日：2006-12-19

申请号：US10718426

申请日：2003-11-20

申请人： Karim S. Boutros ,  Nasser H. Karam ,  Dimitri D. Krut ,  Moran Haddad

发明人： Karim S. Boutros ,  Nasser H. Karam ,  Dimitri D. Krut ,  Moran Haddad

IPC分类号： H01L31/0328 ,  H01L31/117

CPC分类号： H01L31/1852 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02543 ,  H01L21/02546 ,  Y02E10/544

摘要： A semiconductor device having at least one layer of a group III–V semiconductor material epitaxially deposited on a group III–V nucleation layer adjacent to a germanium substrate. By introducing electrical contacts on one or more layers of the semiconductor device, various optoelectronic and microelectronic circuits may be formed on the semiconductor device having similar quality to conventional group III–V substrates at a substantial cost savings. Alternatively, an active germanium device layer having electrical contacts may be introduced to a portion of the germanium substrate to form an optoelectronic integrated circuit or a dual optoelectronic and microelectronic device on a germanium substrate depending on whether the electrical contacts are coupled with electrical contacts on the germanium substrate and epitaxial layers, thereby increase the functionality of the semiconductor devices.

摘要翻译： 具有外延沉积在与锗衬底相邻的III-V族成核层上的III-V族半导体材料的至少一层的半导体器件。 通过在半导体器件的一个或多个层上引入电触点，可以以相当大的成本节约在各种半导体器件上形成各种光电子和微电子电路，其具有与常规III-V族基板相似的质量。 或者，可以将具有电接触的活性锗器件层引入锗衬底的一部分，以在锗衬底上形成光电子集成电路或双光电子和微电子器件，这取决于电接触是否与电接触 锗衬底和外延层，从而增加了半导体器件的功能。