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16 条记录 (耗时 0.051 秒)

    Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor
    1.
    发明授权
    Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor 失效
    具有同步和异步操作的半导体集成电路及其工作方法

    公开(公告)号：US5124589A

    公开(公告)日：1992-06-23

    申请号：US691615

    申请日：1991-04-25

    申请人： Toru Shiomi ,  Shigeki Ohbayashi ,  Atsushi Ohba

    发明人： Toru Shiomi ,  Shigeki Ohbayashi ,  Atsushi Ohba

    IPC分类号： G11C11/414 ,  G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

    摘要： A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.

    摘要翻译： 自定时随机存取存储器件包括可随机访问的存储器电路（7），响应外部时钟信号产生内部时钟信号的时钟发生器（9），响应于内部时钟信号的输入电路（8'） 用于锁存和输出所提供的输入信号;响应于内部时钟信号的输出电路（11'），用于锁存和输出来自存储器件的输出;以及电路（81,82,85,86; 115,116,124， 响应于用于禁止输入电路和输出电路的锁存功能的通过状态指定信号（TH，THM）的控制信号（125; 135,136,144,145）。 可以响应于通过状态指定信号，在与外部提供的时钟信号同步操作的模式和与外部提供的时钟信号异步操作的另一模式之间切换存储​​器件。

    Semiconductor memory device capable of driving divided word lines at high speed
    2.
    发明授权
    Semiconductor memory device capable of driving divided word lines at high speed 失效
    能够高速驱动分割字线的半导体存储器件

    公开(公告)号：US5274597A

    公开(公告)日：1993-12-28

    申请号：US767315

    申请日：1991-09-30

    申请人： Shigeki Ohbayashi ,  Atsushi Ohba ,  Toru Shiomi

    发明人： Shigeki Ohbayashi ,  Atsushi Ohba ,  Toru Shiomi

    IPC分类号： G11C11/41 ,  G11C11/418 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

    CPC分类号： G11C11/418

    摘要： A divided word line driving circuit applicable to a static random access memory (SRAM) employing a divided word line method is disclosed. When a divided word line is activated, the potential at the input of an inverter for driving the word line is brought to a low level. When the input signals S1 and S2 are both at a low level, the divided word line is brought to an inactive state. The input of the inverter is charged by a transistor 101 in addition to a transistor 102 which is always on. In other words, transistor 101 contributes to accelerating charging of the input of the inverter. Consequently, the potential of the divided word line is made to rise at high speed, so that access operation at high speed can be achieved. The circuit is implemented with a small number of transistors, so that it becomes also possible to enhance the degree of integration of a SRAM.

    摘要翻译： 公开了一种适用于采用分割字线方法的静态随机存取存储器（SRAM）的分割字线驱动电路。 当分割字线被激活时，用于驱动字线的逆变器的输入端的电位变为低电平。 当输入信号S1和S2都处于低电平时，分割字线处于非活动状态。 除了始终导通的晶体管102之外，反相器的输入由晶体管101充电。 换句话说，晶体管101有助于加速逆变器的输入的充电。 因此，使分割字线的电位高速上升，从而可以实现高速的存取操作。 该电路由少量的晶体管实现，使得还可以提高SRAM的集成度。

    BiCMOS input buffer circuit operable at high speed under less power consumption
    6.
    发明授权
    BiCMOS input buffer circuit operable at high speed under less power consumption 失效
    BiCMOS输入缓冲电路可在较低功耗下高速运行

    公开(公告)号：US5225717A

    公开(公告)日：1993-07-06

    申请号：US802682

    申请日：1991-12-05

    申请人： Toru Shiomi ,  Jun Takahashi

    发明人： Toru Shiomi ,  Jun Takahashi

    IPC分类号： G11C11/413 ,  G11C8/06 ,  H03K19/00 ,  H03K19/0175

    CPC分类号： G11C8/06 ,  H03K19/0016 ,  H03K19/017527

    摘要： An input buffer circuit applicable as a BiCMOS RAM address buffer is disclosed. An improved level shift circuit 59 includes PMOS transistors 14 and 17 for bypassing emitter follower transistors 12 and 15, and NMOS transistors 13 and 16 for constituting a controllable current source Two differential amplifier circuits operating in response to an input signal having an ECL logic amplitude are provided, and emitter follower transistors 12 and 15 are driven by one of them, MOS transistors 13, 14, 16, and 17 are driven by the other. High operating speed is achieved under less current consumption, since emitter follower transistors 12 and 15, and MOS transistors 13, 14, 16, and 17 are driven, respectively.

    摘要翻译： 公开了一种适用于BiCMOS RAM地址缓冲器的输入缓冲电路。 改进的电平移位电路59包括用于旁路射极跟随器晶体管12和15的PMOS晶体管14和17，以及用于构成可控电流源的NMOS晶体管13和16响应于具有ECL逻辑幅度的输入信号而工作的两个差分放大器电路是 并且射极跟随器晶体管12和15由其中之一驱动，MOS晶体管13,14,16和17由另一个驱动。 由于分别驱动射极跟随器晶体管12和15以及MOS晶体管13,14,16和17，所以在较少的电流消耗下实现高工作速度。

    Semiconductor integrated circuit
    7.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06385081B1

    公开(公告)日：2002-05-07

    申请号：US09808181

    申请日：2001-03-15

    申请人： Toru Shiomi

    发明人： Toru Shiomi

    IPC分类号： G11C1100

    CPC分类号： G11C29/50 ,  G11C11/41

    摘要： A semiconductor integrated circuit identifies and salvages defective memory cells producing a dc current error, such as a standby current fault, and thereby improves semiconductor chip yield. During the wafer test stage of the manufacturing process, a positive and negative supply voltage are both applied to the two inverter circuits 8, 9 of the SRAM memory cell 1 to detect defective memory cells where a microshort occurs. The fuse inserted the supply line of the detected defective memory cell is then broken to interrupt applying a positive or negative supply voltage to the defective memory cell, and a redundant memory cell provided in the memory cell array is substituted for the defective memory cell.

    摘要翻译： 半导体集成电路识别并补救产生诸如待机电流故障之类的直流电流误差的有缺陷的存储单元，从而提高半导体芯片的产量。 在制造工艺的晶片测试阶段期间，正电荷和负电源都被施加到SRAM存储单元1的两个反相器电路8,9，以检测发生微型短路的有缺陷的存储单元。 插入检测到的有缺陷的存储单元的电源线的保险丝然后断开，以中断向缺陷存储单元施加正电源或负电源电压，并且设置在存储单元阵列中的冗余存储单元代替有缺陷的存储单元。

    Bipolar cross-coupled memory cells having improved immunity to soft errors
    8.
    发明授权
    Bipolar cross-coupled memory cells having improved immunity to soft errors 失效
    具有改善的对软错误的免疫性的双极交叉耦合存储器单元

    公开(公告)号：US5095355A

    公开(公告)日：1992-03-10

    申请号：US554988

    申请日：1990-07-17

    申请人： Toru Shiomi ,  Kakutaro Suda ,  Tetsuo Higuchi

    发明人： Toru Shiomi ,  Kakutaro Suda ,  Tetsuo Higuchi

    IPC分类号： H01L27/06 ,  H01L21/8229 ,  H01L27/102

    CPC分类号： H01L27/1025

    摘要： A bipolar RAM comprising a plurality of memory cells formed of cross-coupled bipolar transistors and a peripheral bipolar circuit formed of bipolar transistor, provided with an epitaxial layer which is to be the collector region of the bipolar transistor in the memory cell portion which is thinner and has higher impurity density than the epitaxial layer which is to be the collector region of a bipolar transistor in the peripheral circuit.

    摘要翻译： 一种双极型RAM，包括由交叉耦合双极晶体管形成的多个存储单元和由双极晶体管形成的外围双极电路，该外围层设置在存储单元部分中的双极晶体管的集电极区域，该外延层较薄 并且具有比作为外围电路中的双极晶体管的集电极区域的外延层更高的杂质浓度。

    Bi-CMOS type of semiconductor memory device
    9.
    发明授权
    Bi-CMOS type of semiconductor memory device 失效
    Bi-CMOS型半导体存储器件

    公开(公告)号：US4897820A

    公开(公告)日：1990-01-30

    申请号：US156432

    申请日：1988-02-16

    申请人： Toru Shiomi ,  Kenji Anami

    发明人： Toru Shiomi ,  Kenji Anami

    IPC分类号： G11C11/415 ,  G11C8/06 ,  G11C8/10

    CPC分类号： G11C8/06 ,  G11C8/10

    摘要： An address buffer decoder comprises n address buffer circuits, a decoder circuit, 2.sup.n level converting circuits and 2.sup.n driver circuits. Each of the address buffer circuits has an input terminal receiving an address signal of an ECL level. The decoder circuit comprises a plurality of output terminals and a plurality of inverted output terminals in each of the address buffer circuits and a plurality of interconnections. A selecting signal of an "L" level is outputted to one of the plurality of interconnections depending on combinations of address signals inputted to the plurality of address buffer circuits. The selecting signal is converted into a signal of an MOS level by each of the level converting circuits. Current of the signal of the MOS level is amplified by each of the driver circuits. The signal of the MOS level is outputted to a corresponding selecting line.

    摘要翻译： 一个地址缓冲器解码器包括n个地址缓冲器电路，一个解码器电路，2n个电平转换电路和2n个驱动电路。 每个地址缓冲电路具有接收ECL电平的地址信号的输入端。 解码器电路包括在每个地址缓冲器电路中的多个输出端子和多个反相输出端子以及多个互连。 根据输入到多个地址缓冲器电路的地址信号的组合，将“L”电平的选择信号输出到多个互连中的一个。 通过各电平转换电路将选择信号转换为MOS电平的信号。 MOS电平的信号电流被每个驱动电路放大。 MOS电平的信号被输出到相应的选择线。

    Semiconductor memory device capable of repairing small leak failure
    10.
    发明授权
    Semiconductor memory device capable of repairing small leak failure 失效

    公开(公告)号：US06466506B2

    公开(公告)日：2002-10-15

    申请号：US09793768

    申请日：2001-02-27

    申请人： Toru Shiomi

    发明人： Toru Shiomi

    IPC分类号： G11C800

    CPC分类号： G11C29/83 ,  G11C11/41 ,  G11C11/412 ,  G11C29/08 ,  G11C29/50

    摘要： A power supply potential GNDP as a substrate potential of two N-channel MOS transistors constructing an SRAM transistor memory cell is enabled to be controlled independent of a ground potential GNDM as a source potential of the N-channel MOS transistors. In the case where a standby current failure occurs, by weakening the driving ability of the N-channel MOS transistors by a substrate effect, the failure can be found in a functional test. A defective memory cell as a cause of the standby current failure, in which a small leak occurs can be specified and is replaced by a redundant memory cell, thereby enabling the yield to be improved.