公开(公告)号：US5942786A

公开(公告)日：1999-08-24

申请号：US767824

申请日：1996-12-17

Applicant: Shing-Ren Sheu ,  Cheng-Chih Kung

Inventor： Shing-Ren Sheu ,  Cheng-Chih Kung

IPC: H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/112

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.

公开(公告)号：US06417548B1

公开(公告)日：2002-07-09

申请号：US09356679

申请日：1999-07-19

Applicant: Shing-Ren Sheu ,  Cheng-Chih Kung

Inventor： Shing-Ren Sheu ,  Cheng-Chih Kung

IPC: H01L2976

CPC classification number: H01L27/11233 ,  H01L27/1052 ,  H01L27/112

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.

Abstract translation: 掩模ROM通过选择FET阵列中每个FET的栅极的功函数来存储信息。 一些FET的多晶硅栅极被掺杂为N型，并且其它FET的栅极被掺杂P型以形成具有不同功函数的栅极，从而形成具有不同阈值电压的FET。 该ROM由在衬底中形成的掩埋N +位线的平行阵列，沉积在位线上的栅极氧化物层和沉积在栅极氧化物上的多晶硅层组成。 多晶硅是覆盖掺杂P型，然后形成编码掩模，其中编码掩模中的开口暴露多晶硅的区域，以形成具有低阈值电压的FET的栅极。 砷或磷通过掩模开口掺杂到多晶硅中。 去除掩模，沉积诸如硅化钨的导电材料层，并且将多晶硅和导电材料形成为ROM的字线。 ROM的字线用作FET的栅极，位线用作FET的源极和漏极。

公开(公告)号：US6054353A

公开(公告)日：2000-04-25

申请号：US746855

申请日：1996-11-18

Applicant: Shing-Ren Sheu ,  Cheng-Chih Kung

Inventor： Shing-Ren Sheu ,  Cheng-Chih Kung

IPC: H01L21/8246 ,  H01L21/8234

CPC classification number: H01L27/11293 ,  H01L27/1126

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer. The implantation converts individual gate electrodes from N-type to P-type to alter the threshold voltage of the selected transistors. Relatively few additional processing steps are needed after the programming to complete the ROM.

Abstract translation: 掩模ROM通过在ROM的制造中的晚期阶段选择FET的阵列中的每个FET的栅极的功函数来存储信息。 一些FET的多晶硅栅极被掺杂为N型，并且其它FET的栅极被掺杂P型以形成具有不同功函数的栅极，从而形成具有不同阈值电压的FET。 该ROM由在衬底中形成的掩埋N +位线的平行阵列，沉积在位线上的栅极氧化物层和沉积在栅极氧化物上的多晶硅层组成。 多晶硅是覆盖N掺杂的，栅极通过光刻法定义，然后在栅电极上形成自对准的硅化物层。 然后在栅电极上形成绝缘层。 ROM的编程通过在绝缘层上形成掩模然后通过掩模中的开口通过绝缘层和硅化物层注入离子并进入多晶硅层来实现。 注入将单个栅电极从N型转换为P型，以改变所选晶体管的阈值电压。 在编程完成ROM之后，需要较少的附加处理步骤。

公开(公告)号：US20090026576A1

公开(公告)日：2009-01-29

申请号：US11782154

申请日：2007-07-24

Applicant: Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

Inventor： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L23/5252 ,  H01L21/26586 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions.

Abstract translation: 提供反熔丝。 反熔丝包括衬底，设置在衬底上的栅极，夹在衬底和栅极之间的栅极电介质层以及在栅极的相应侧的衬底中的两个源极/漏极区域。 栅极和衬底具有相同的导电类型，但是栅极和衬底的导电类型与两个源极/漏极区的导电类型不同。

公开(公告)号：US5576573A

公开(公告)日：1996-11-19

申请号：US454701

申请日：1995-05-31

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/112 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/112 ,  H01L29/42368 ,  Y10S438/981

Abstract: A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

Abstract translation: 一种用于掩模ROM器件的多状态存储单元。 源极/漏极区域沿着衬底和位线的平面上沿着第一方向延伸的条带布置在衬底上。 栅极氧化物层沿着第二方向布置在基板上。 栅极电极分别形成在每个栅极氧化物层的顶部上，作为沿第二方向延伸的条带。 栅极氧化物层具有多个选定的厚度，以差分系列排列。 每个晶体管沟道区以及它们相应的一个源极/漏极对，顶部的栅极氧化物层和进一步在其顶部的栅电极构成一个存储单元，其可以使其阈值电压在 差分系列的厚度允许存储用于存储器单元的多位等效的存储器内容。

公开(公告)号：US20090322360A1

公开(公告)日：2009-12-31

申请号：US12145518

申请日：2008-06-25

Applicant: Shing-Ren Sheu ,  Chun-Chieh Huang

Inventor： Shing-Ren Sheu ,  Chun-Chieh Huang

IPC: G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2831

Abstract: A test system provides defect information rapidly and systematically. The test system includes a plurality of test units arranged in a matrix, a plurality of bit lines and a plurality of word lines. Each test unit has a first terminal and a second terminal. Each second terminal of the test unit is electrically connected to a ground point. The first terminals of the test units are electrically connected to the bit lines. The word lines are coupled to the test units. Defects in the each test unit can be identified by providing voltages to the bit lines and the word lines. Accordingly, defects in various devices of an integrated circuit can be detected rapidly and systematically by applying signals to the test system.

Abstract translation: 测试系统快速有系统地提供缺陷信息。 测试系统包括以矩阵，多个位线和多个字线布置的多个测试单元。 每个测试单元具有第一端子和第二端子。 测试单元的每个第二端子电连接到接地点。 测试单元的第一个端子电连接到位线。 字线耦合到测试单元。 可以通过向位线和字线提供电压来识别每个测试单元中的缺陷。 因此，可以通过向测试系统施加信号来快速且系统地检测集成电路的各种装置中的缺陷。

公开(公告)号：US20090029541A1

公开(公告)日：2009-01-29

申请号：US12211608

申请日：2008-09-16

Applicant: Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

Inventor： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

IPC: H01L21/44

CPC classification number: H01L23/5252 ,  H01L21/26586 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer.

Abstract translation: 制造抗熔丝的方法包括首先在具有第一导电类型的衬底上形成电介质层。 接下来，在电介质层上形成导电层。 然后执行第一离子注入工艺，使得导电层具有第一导电类型。 此后，对导电层和电介质层进行构图以形成栅极和栅极电介质层。 栅极和栅极电介质层一起构成栅极结构。 最后，具有第二导电类型的两个源极/漏极区域形成在栅极的相应侧的衬底中。 此外，编制反熔丝的方法包括首先向栅极施加电压以分解栅极电介质层。 然后对栅极和衬底进行电导或在栅极电介质层击穿之后在P / N结中形成P / N正向偏压。

公开(公告)号：US07026234B2

公开(公告)日：2006-04-11

申请号：US10709940

申请日：2004-06-08

Applicant: Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

Inventor： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

IPC: H01L21/44 ,  H01L29/40

CPC classification number: H01L24/13 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract translation: 衬底上的寄生电容防止虚拟焊料凸块结构具有至少一个形成在衬底上的导电层，用于覆盖导电层的电介质层，形成在电介质层上的凸块下金属层（UBM层）和 焊料凸块形成在UBM层上。

公开(公告)号：US5691234A

公开(公告)日：1997-11-25

申请号：US511065

申请日：1995-08-03

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/02 ,  H01L21/28

CPC classification number: H01L27/0255

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract translation: 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

公开(公告)号：US5429975A

公开(公告)日：1995-07-04

申请号：US140401

申请日：1993-10-25

Applicant: Shing-Ren Sheu ,  Chen-Chiu Hsue ,  Chen-Hui Chung

Inventor： Shing-Ren Sheu ,  Chen-Chiu Hsue ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112 ,  H01L27/00 ,  H01L21/70

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A ROM device with an array of cells and a method of manufacturing comprises: forming closely spaced conductors in the surface of a semiconductor substrate having a second type of background impurity. Insulation is formed on the substrate. Closely spaced, parallel, conductors on the insulation are arranged orthogonally to the line regions. Glass insulation is formed over the conductors. Reflowing the glass insulation, forming contacts and forming a metal layer on the glass insulation follow. A resist is formed, exposed forming a resist metal pattern, then etching through the resist to pattern metal and removing the resist. Depositing a resist onto the patterned metal, and exposing the second resist with a custom code pattern, developing the resist into a mask follow. Impurity ions are implanted into the substrate adjacent to the conductors through the openings in a second resist layer. The device is passivated followed by activating the implanted impurity ions by annealing the device at a temperature less than or equal to about 520.degree. C. in a forming gas or N.sub.2 atmosphere.

Abstract translation: 具有单元阵列的ROM器件和制造方法包括：在具有第二类背景杂质的半导体衬底的表面中形成紧密间隔的导体。 在基板上形成绝缘体。 绝缘体上紧密间隔开的平行导体与线路区域正交配置。 在导体上形成玻璃绝缘体。 玻璃绝缘回流，形成接触并在玻璃绝缘上形成金属层。 形成抗蚀剂，暴露形成抗蚀剂金属图案，然后通过抗蚀剂蚀刻图案金属并除去抗蚀剂。 将抗蚀剂沉积到图案化的金属上，并用定制代码图案曝光第二抗蚀剂，将抗蚀剂显影成掩模。 通过第二抗蚀剂层中的开口将杂质离子注入邻近导体的衬底中。 钝化该器件，然后在形成气体或N 2气氛中，在小于或等于约520℃的温度下对器件进行退火来激活注入的杂质离子。