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9 条记录 (耗时 0.026 秒)

    Emergency shutdown system for controlling industrial robot
    1.
    发明授权
    Emergency shutdown system for controlling industrial robot 失效
    用于控制工业机器人的紧急停机系统

    公开(公告)号：US5363474A

    公开(公告)日：1994-11-08

    申请号：US30291

    申请日：1993-03-18

    申请人： Shinichi Sarugaku ,  Toru Kurenuma ,  Takeshi Andoh ,  Masami Otomo ,  Kyoichi Kawasaki

    发明人： Shinichi Sarugaku ,  Toru Kurenuma ,  Takeshi Andoh ,  Masami Otomo ,  Kyoichi Kawasaki

    IPC分类号： B25J9/22 ,  B25J9/16 ,  B25J9/18 ,  B25J13/08 ,  B25J19/06 ,  G05B19/42 ,  G05B19/425 ,  G06F15/00

    CPC分类号： G05B19/425 ,  B25J9/1674 ,  G05B2219/36399 ,  G05B2219/36473 ,  G05B2219/42123

    摘要： A system for controlling an industrial robot, which is simplified in operation and capable of direct-teaching safely all the time. The system is provided with means (131 and 132) for monitoring a magnitude of an external force applied to the forward end of a hand during direct teaching, so that the motion of the robot can be forcibly restricted when the external force reaches a predetermined value of thereabove. Furthermore, when the system is operated to be set in a direct teach mode, a process (136) of correcting the offset of a force sensor is performed automatically. By monitoring a force detected by the force sensor, the discrimination is made as to whether an external force to operate the robot at an abnormal speed is applied to the robot or not, and when the external force becomes higher than a reference value, a mode of prohibiting the operation of the robot by the external force (position control mode) is set, or current supplied to a servo motor is cut off to prevent the robot from going into the erroneous operation due to an erroneous control.

    摘要翻译： PCT No.PCT / JP92 / 00616 Sec。 371日期1993年3月18日 102（e）1993年3月18日PCT提交1992年5月14日PCT公布。 出版物WO92 / 21076 日期：1992年11月26日。一种控制工业机器人的系统，操作简单，能够安全地直接教学。 该系统设置有用于在直接教导期间监测施加到手的前端的外力的大小的装置（131和132），使得当外力达到预定值时可以强制地限制机器人的运动 在上面。 此外，当系统被操作以被设置在直接示教模式时，自动执行校正力传感器的偏移的处理（136）。 通过监视由力传感器检测到的力，判断是否将机器人以异常速度操作的外力施加到机器人，并且当外力变得高于基准值时，模式 设定通过外力（位置控制模式）禁止机器人的操作，或者切断供给伺服电动机的电流，以防止机器人由于错误的控制而进入错误操作。

    Semiconductor device having a load less four transistor cell
    2.
    发明授权
    Semiconductor device having a load less four transistor cell 失效
    具有负载少于四个晶体管单元的半导体器件

    公开(公告)号：US06724650B2

    公开(公告)日：2004-04-20

    申请号：US10270483

    申请日：2002-10-16

    申请人： Takeshi Andoh

    发明人： Takeshi Andoh

    IPC分类号： G11C1100

    CPC分类号： G11C11/412

    摘要： A unit memory cell comprises first and second field effect transistors of a first conduction type, third and fourth field effect transistors of a second conduction type, and first and second resistance elements. A gate electrode of the first transistor is connected to a second node, a gate electrode of the second transistor is connected to a first node, a series connected structure constructed by connecting a source/drain path of the third transistor and the first resistance element in series is connected between the first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of the fourth transistor and the second resistance element in series is connected between the second node and a second bit line paired with the first bit line, and both gate electrodes of the third and fourth field effect transistors are connected to a word line.

    摘要翻译： 单元存储单元包括第一导电类型的第一和第二场效应晶体管，第二导电类型的第三和第四场效应晶体管以及第一和第二电阻元件。 第一晶体管的栅电极连接到第二节点，第二晶体管的栅电极连接到第一节点，串联连接结构通过将第三晶体管的源/漏路径与第一电阻元件连接 串联连接在第一节点和第一位线之间，通过将第四晶体管的源极/漏极路径和第二电阻元件串联连接而构成的串联结构连接在第二节点和与第二节点配对的第二位线之间 第一位线和第三和第四场效应晶体管的两个栅电极连接到字线。

    Electrostatic discharge protection circuit
    4.
    发明授权
    Electrostatic discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US06507469B2

    公开(公告)日：2003-01-14

    申请号：US09880034

    申请日：2001-06-14

    申请人： Takeshi Andoh

    发明人： Takeshi Andoh

    IPC分类号： H02H900

    CPC分类号： H01L27/0255 ,  H01L27/0266 ,  H01L27/0288

    摘要： In an electrostatic protection circuit of the present invention, a trigger voltage for causing snapback operation in MOSFET is reduced and circuit elements with low breakdown voltages can be protected. A protection nMOSFET having a drain connected to an input/output terminal and a source and a substrate that are grounded is provided. A diode array, composed of at least one diode, is connected in series in a forward direction between the gate of the protection nMOSFET and the input/output terminal. Finally, a resistor is connected between the gate of the protection nMOSFET and ground.

    摘要翻译： 在本发明的静电保护电路中，降低了在MOSFET中引起快速恢复操作的触发电压，并且可以保护具有低击穿电压的电路元件。 提供了具有连接到输入/输出端子的漏极和接地的源极和衬底的保护nMOSFET。 由至少一个二极管组成的二极管阵列在保护nMOSFET的栅极和输入/输出端子之间沿正向串联连接。 最后，在保护nMOSFET的栅极和地之间连接一个电阻。

    Fabrication method of semiconductor device with CMOS structure
    5.
    发明授权
    Fabrication method of semiconductor device with CMOS structure 失效
    具有CMOS结构的半导体器件的制造方法

    公开(公告)号：US5908309A

    公开(公告)日：1999-06-01

    申请号：US67861

    申请日：1998-04-28

    申请人： Takeshi Andoh

    发明人： Takeshi Andoh

    IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/04 ,  H01L21/425

    CPC分类号： H01L21/823835 ,  Y10S438/919

    摘要： A fabrication method of a semiconductor device with the CMOS structure, which suppresses the sheet resistance of silicide layers of a refractory metal in an n-channel MOSFET at a satisfactorily low level while preventing the junction leakage current in a p-channel MOSFET from increasing. An n-type dopant is selectively ion-implanted into surface areas of a first pair of n-type source/drain regions and a surface area of a first gate electrode in an NMOS region at a first acceleration energy, thereby forming a first plurality of amorphous regions in the NMOS region. The n-type dopant is ion-implanted into surface areas of the second pair of p-type source/drain regions and a surface area of the second gate electrode in a PMOS region at a second acceleration energy lower than the first acceleration energy, thereby forming second plurality of amorphous regions in the PMOS region. The second acceleration energy is set in such a way that bottoms of the second pair of p-type source/drain regions in the PMOS region are not substantially shifted due to ion implantation of the n-type dopant for forming the second plurality of amorphous regions.

    摘要翻译： 具有CMOS结构的半导体器件的制造方法，其以令人满意的低电平抑制了n沟道MOSFET中难熔金属的硅化物层的薄层电阻，同时防止p沟道MOSFET中的结漏电流增加。 n型掺杂剂以第一加速能量选择性地离子注入第一对n型源极/漏极区域的表面区域和NMOS区域中的第一栅极电极的表面积，从而形成第一多个 NMOS区域中的非晶区域。 n型掺杂剂以第二加速能量低于第一加速能量离子注入到第二对p型源极/漏极区的表面区域和PMOS区域中的第二栅电极的表面积，从而 在PMOS区域中形成第二多个非晶区域。 第二加速能量被设定为使得PMOS区域中的第二对p型源极/漏极区域的底部由于用于形成第二多个非晶区域的n型掺杂剂的离子注入而基本上不偏移 。

    Viterbi decoder with pipelined ACS circuits
    6.
    发明授权
    Viterbi decoder with pipelined ACS circuits 失效
    维特比解码器与流水线ACS电路

    公开(公告)号：US06259749B1

    公开(公告)日：2001-07-10

    申请号：US08939911

    申请日：1997-09-29

    申请人： Takeshi Andoh

    发明人： Takeshi Andoh

    IPC分类号： H03D100

    CPC分类号： H03M13/6561 ,  H03M13/3961 ,  H03M13/4107

    摘要： In a Viterbi decoder, a sequence of branch metrics is derived from a received convolutional codeword sequence. The branch metric sequence is divided and supplied to add/compare/select (ACS) circuits where the divided branch metric sequences added to previous path metrics. Path metric sequences of maximum likelihood paths are determined by the ACS circuits and indicators identifying the maximum likelihood paths are produced. A pipelining circuit is provided for reordering, or pipelining state metrics of the path metrics of the maximum likelihood paths and supplying the pipelined state metrics to the ACS circuits. The indicators from the ACS circuits are used to recover an original bit sequence.

    摘要翻译： 在维特比解码器中，从接收的卷积码字序列导出分支度量序列。 分支度量序列被分割并提供给添加/比较/选择（ACS）电路，其中分配的分支度量序列被添加到先前的路径度量。 最大似然路径的路径度量序列由ACS电路确定，并且产生识别最大似然路径的指示符。 提供流水线电路用于重新排序或流水线最大似然路径的路径度量的状态度量，并将流水线状态度量提供给ACS电路。 来自ACS电路的指示器用于恢复原始位序列。

    Semiconductor storage device
    8.
    发明申请
    Semiconductor storage device 审中-公开
    半导体存储设备

    公开(公告)号：US20050068832A1

    公开(公告)日：2005-03-31

    申请号：US10938635

    申请日：2004-09-13

    申请人： Takeshi Andoh

    发明人： Takeshi Andoh

    IPC分类号： G11C11/418 ,  G11C5/14 ,  G11C7/04 ,  G11C8/08 ,  G11C11/41 ,  G11C11/413 ,  G11C7/00

    CPC分类号： G11C7/04 ,  G11C5/147 ,  G11C8/08

    摘要： A semiconductor storage device detects a temperature T0 at which an output voltage Vtemp of the temperature detecting circuit equals to an output voltage Vref0 of the reference voltage generating circuit. In the lower temperature range lower than the temperature T0, the value of the reference voltage Vref is reduced by a preset voltage ΔV from an external power supply voltage Vdd by a variable voltage generating circuit. The lowered voltage (Vdd−ΔV) is applied to the word line WL of the memory cell via the word line driver as a variable power supply voltage Vcp.

    摘要翻译： 半导体存储装置检测温度检测电路的输出电压Vtemp等于基准电压产生电路的输出电压Vref0的温度T0。 在低于温度T0的较低温度范围内，参考电压Vref的值通过可变电压发生电路从外部电源电压Vdd减小预设电压DeltaV。 降低的电压（Vdd-ΔV）经由字线驱动器作为可变电源电压Vcp施加到存储单元的字线WL。

    Static semiconductor memory device
    9.
    发明授权
    Static semiconductor memory device 失效
    静态半导体存储器件

    公开(公告)号：US5336914A

    公开(公告)日：1994-08-09

    申请号：US901021

    申请日：1992-06-19

    申请人： Takeshi Andoh

    发明人： Takeshi Andoh

    IPC分类号： H01L27/11 ,  H01L29/06 ,  H01L29/78

    CPC分类号： H01L27/1108

    摘要： A MOS SRAM comprising memory cells capable of taking up less areas is disclosed. The flip-flop of a memory cell is connected to a pair of bit lines through a pair of transfer MOSFETs each corresponding to a bit line. At least one, preferably one on the flip-flop side, of the source and drain regions of each transfer MOSFET has a higher resistance. This enables to prevent damage of data which may happen during readout even in the case of use of finer word lines, and therefore contributes to the realization of the SRAM cell taking up relatively less area.

    摘要翻译： 公开了包括能够占用较少面积的存储器单元的MOS SRAM。 存储单元的触发器通过一对对应于位线的传输MOSFET连接到一对位线。 每个传输MOSFET的源区和漏极区中至少一个，优选一个在触发器侧上具有较高的电阻。 这使得即使在使用更细的字线的情况下也能够防止在读出期间可能发生的数据的损坏，并且因此有助于SRAM单元占用相对较小面积的实现。