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    Method of etching high aspect ratio openings
    1.
    发明授权
    Method of etching high aspect ratio openings 失效
    蚀刻高纵横比开口的方法

    公开(公告)号：US06743727B2

    公开(公告)日：2004-06-01

    申请号：US09874109

    申请日：2001-06-05

    申请人： Gangadhara S. Mathad ,  Siddhartha Panda ,  Rajiv M. Ranade

    发明人： Gangadhara S. Mathad ,  Siddhartha Panda ,  Rajiv M. Ranade

    IPC分类号： H01L2100

    CPC分类号： H01L21/30655 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/76224

    摘要： A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

    摘要翻译： 在硅衬底中蚀刻深，高纵横比开口的方法包括使用包含含溴气体，含氧气体和第一含氟气体的第一气体混合物形成的第一等离子体蚀刻衬底。 用第一气体混合物的蚀刻工艺产生侧壁钝化沉积物，其沉积在开口入口附近。 为了减少这种积累并且为了提高平均蚀刻速率，通过使用含有硅烷和第二含氟气体的混合物形成第二等离子体来周期性地减薄侧壁钝化沉积物。 在整个工艺期间，衬底保持在相同的等离子体反应器室中，并且在稀化步骤期间连续维持等离子体。 可以使用重复的蚀刻和变薄循环来产生大于40倍宽度的孔。

    Method to increase the etch rate and depth in high aspect ratio structure
    2.
    发明授权
    Method to increase the etch rate and depth in high aspect ratio structure 失效
    在高纵横比结构中增加蚀刻速率和深度的方法

    公开(公告)号：US06709917B2

    公开(公告)日：2004-03-23

    申请号：US10145230

    申请日：2002-05-13

    申请人： Siddhartha Panda ,  Rajiv M. Ranade ,  Gangadhara S. Mathad

    发明人： Siddhartha Panda ,  Rajiv M. Ranade ,  Gangadhara S. Mathad

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L21/3065

    摘要： A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.

    摘要翻译： 一种在半导体衬底中制造高深宽比深沟槽的方法，包括在蚀刻蚀刻期间减少钝化膜的形成，包括使要形成深沟槽的衬底与氟差的接触的第一步骤 或低浓度的蚀刻剂气体等离子体中的氟气，用于蚀刻高纵横比深沟槽，随后是增加含氟气体的浓度以产生富氟等离子体同时降低室内压力的第二步骤 电抗器和RF功率。 优选地，在以交替方式蚀刻深沟槽期间周期性地引入第二步骤。

    Method to achieve increased trench depth, independent of CD as defined by lithography
    3.
    发明授权
    Method to achieve increased trench depth, independent of CD as defined by lithography 失效
    实现增加沟槽深度的方法，与光刻所定义的CD无关

    公开(公告)号：US06821864B2

    公开(公告)日：2004-11-23

    申请号：US10093789

    申请日：2002-03-07

    申请人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    发明人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    IPC分类号： H01L2176

    CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/76895

    摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

    摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。

    Method to achieve increased trench depth, independent of CD as defined by lithography
    4.
    发明授权
    Method to achieve increased trench depth, independent of CD as defined by lithography 失效
    实现增加沟槽深度的方法，与光刻所定义的CD无关

    公开(公告)号：US07144769B2

    公开(公告)日：2006-12-05

    申请号：US10899758

    申请日：2004-07-27

    申请人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    发明人： Kevin K. Chan ,  Subhash B. Kulkarni ,  Gangadhara S. Mathad ,  Rajiv M. Ranade

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/76224 ,  H01L21/76895

    摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

    摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。

    CONTROL OF DRY CLEAN PROCESS IN WAFER PROCESSING
    6.
    发明申请
    CONTROL OF DRY CLEAN PROCESS IN WAFER PROCESSING 审中-公开
    干法处理干燥过程控制

    公开(公告)号：US20080190446A1

    公开(公告)日：2008-08-14

    申请号：US11674218

    申请日：2007-02-13

    申请人： Rajiv M. Ranade ,  Subhash B. Kulkarni ,  Ole Krogh ,  Sukesh Patel

    发明人： Rajiv M. Ranade ,  Subhash B. Kulkarni ,  Ole Krogh ,  Sukesh Patel

    IPC分类号： B08B6/00

    CPC分类号： H01L21/6833 ,  H01L21/67028 ,  H01L21/67051

    摘要： A “wafer-less” etch chamber cleaning method varies the capacitance applied to radio frequency components of the chuck that is within the etch chamber (varies impedance of the chuck) so as to cause electric field lines within the etch chamber to terminate (bend) away from the chuck. Then the etch chamber can be cleaned using a very aggressive etch chemistry (e.g., NF3) that would otherwise damage the chuck; however, the electric field lines protect the chuck from the etch chemistry. The capacitance is varied according to a pre-established model. Further, the process evaluates the effectiveness of the pre-established model to produce feedback and constantly adjusts the pre-established model to increase the effectiveness of the cleaning process (according to the feedback).

    摘要翻译： “无晶圆”蚀刻室清洁方法改变施加到蚀刻室内的卡盘的射频分量（改变卡盘的阻抗）的电容，以使蚀刻室内的电场线终止（弯曲） 远离卡盘 然后可以使用非常有侵蚀性的蚀刻化学品（例如，NF 3 3）清洁蚀刻室，否则会损坏卡盘; 然而，电场线路保护卡盘免受蚀刻化学物质的影响。 电容根据预先建立的模型而变化。 此外，该过程评估预先建立的模型的有效性以产生反馈并且不断调整预先建立的模型以增加清洁过程的有效性（根据反馈）。

    USE OF AN ORGANIC PLANARIZING MASK FOR CUTTING A PLURALITY OF GATE LINES
    7.
    发明申请
    USE OF AN ORGANIC PLANARIZING MASK FOR CUTTING A PLURALITY OF GATE LINES 失效
    使用有机平面化掩模切割大量的浇口线

    公开(公告)号：US20130143397A1

    公开(公告)日：2013-06-06

    申请号：US13612981

    申请日：2012-09-13

    申请人： Nicholas C.M. Fuller ,  Pratik P. Joshi ,  Mahmoud Khojasteh ,  Rajiv M. Ranade ,  George G. Totir

    发明人： Nicholas C.M. Fuller ,  Pratik P. Joshi ,  Mahmoud Khojasteh ,  Rajiv M. Ranade ,  George G. Totir

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/31133 ,  H01L21/823437 ,  H01L21/823828

    摘要： An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.

    摘要翻译： 在其上包括多条栅极线的半导体衬底上形成有机平面化层（OPL）。 每个栅极线包括至少一个高k栅极电介质和金属栅极。 然后将其中形成有至少一种图案的图案化的光致抗蚀剂定位在OPL的顶部。 光致抗蚀剂中的至少一个图案垂直于每个栅极线。 然后通过蚀刻将图案转移到OPL和每个下面的栅极线的部分，以提供多个栅极堆叠，每个栅极堆叠包括至少一个高k栅极电介质部分和金属栅极部分。 然后使用一系列步骤除去图案化的光致抗蚀剂和剩余的OPL层，所述步骤包括首先与第一酸接触，第二次与含铈水溶液接触，并且与第二次酸接触。

    MRAM MTJ stack to conductive line alignment method
    8.
    发明授权
    MRAM MTJ stack to conductive line alignment method 失效
    MRAM MTJ堆叠到导线对准方法

    公开(公告)号：US06858441B2

    公开(公告)日：2005-02-22

    申请号：US10234864

    申请日：2002-09-04

    申请人： Joachim Nuetzel ,  Xian J. Ning ,  Kia-Seng Low ,  Gill Yong Lee ,  Rajiv M. Ranade ,  Ravikumar Ramachandran

    发明人： Joachim Nuetzel ,  Xian J. Ning ,  Kia-Seng Low ,  Gill Yong Lee ,  Rajiv M. Ranade ,  Ravikumar Ramachandran

    IPC分类号： H01L23/544 ,  H01L27/22 ,  H01L21/28

    CPC分类号： H01L27/222 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

    摘要： A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).

    摘要翻译： 一种制造电阻半导体存储器件（100）的方法，包括在工件（30）上沉积绝缘层（132），并且限定用于多个对准标记（128）和多条导线（112）的图案， 在绝缘层（132）内。 导电材料沉积在晶片上以填充对准标记（128）和导线（112）图案。 绝缘层（132）顶表面被化学机械抛光以从绝缘层（132）去除多余的导电材料并形成导电线（112），同时留下导电材料留在对准标记（128）内。 掩模层（140）形成在导电线（112）之上，并且导电材料的至少一部分从对准标记（128）内移除。 对准标记（128）用于电阻式存储器件（100）的后续沉积层的对准。

    Method and system for line-dimension control of an etch process
    9.
    发明授权
    Method and system for line-dimension control of an etch process 失效
    用于蚀刻工艺的线尺寸控制的方法和系统

    公开(公告)号：US07700378B2

    公开(公告)日：2010-04-20

    申请号：US11872098

    申请日：2007-10-15

    申请人： Gary Walter Behm ,  Teresita Quitua Magtoto ,  Rajiv M. Ranade

    发明人： Gary Walter Behm ,  Teresita Quitua Magtoto ,  Rajiv M. Ranade

    IPC分类号： H01L21/66

    CPC分类号： H01J37/32082 ,  H01J37/32935

    摘要： A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.

    摘要翻译： 一种用于控制蚀刻特征尺寸的方法和系统。 该方法包括：测量形成在基板上的层的顶表面上的掩模特征以获得掩模特征尺寸值; 以及基于掩模特征尺寸值，掩模特征尺寸目标值，等离子体蚀刻工具的选定的射频加电时间的总和，计算掩模修整等离子体蚀刻时间，因为发生到等离子体的室或室的事件 用于等离子体蚀刻该层的蚀刻工具，以及用于在该层的等离子体蚀刻期间该层不被掩模特征保护的层形成的层特征的蚀刻偏置目标。