公开(公告)号：US10192838B2

公开(公告)日：2019-01-29

申请号：US15411204

申请日：2017-01-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Lung Chuang ,  Po-Yi Wu ,  Meng-Tsung Lee ,  Yih-Jenn Jiang

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/31

Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.

公开(公告)号：US20170133337A1

公开(公告)日：2017-05-11

申请号：US15411204

申请日：2017-01-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Lung Chuang ,  Po-Yi Wu ,  Meng-Tsung Lee ,  Yih-Jenn Jiang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3157 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.