公开(公告)号：US08981540B2

公开(公告)日：2015-03-17

申请号：US13922904

申请日：2013-06-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Yu Chiang ,  Wen-Jung Chiang ,  Hsing-Hung Lee

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49589 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00

Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.

Abstract translation: 公开了一种封装结构，其包括：具有形成在其下侧并填充有电介质材料的凹部的载体; 半导体元件，其设置在所述载体的上侧并电连接到所述载体; 以及密封剂，其形成在用于封装半导体元件的载体的上侧。 其中，电介质材料从密封剂暴露出来。 因此，当载体设置在电路板上时，电介质材料夹在载体的下侧和电路板之间以形成去耦电容器，从而提高电力完整性。

公开(公告)号：US09305885B2

公开(公告)日：2016-04-05

申请号：US13960064

申请日：2013-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tai-Tsung Hsu ,  Cheng-Yu Chiang ,  Miao-Wen Chen ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/552 ,  H01L21/00 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/428 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/1815

Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

Abstract translation: 提供一种多芯片封装结构，包括具有接地结构的基板; 两个半导体元件设置在基板上并与其电连接; 形成在所述基板上并封装半导体元件的密封剂，其中所述密封剂具有形成在所述半导体元件之间的多个圆形孔; 以及形成在每个圆孔中的电磁屏蔽结构，并连接到接地结构以实现电磁屏蔽效果。 还提供了一种用于形成多芯片封装的方法。

公开(公告)号：US20140231972A1

公开(公告)日：2014-08-21

申请号：US13960064

申请日：2013-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tai-Tsung Hsu ,  Cheng-Yu Chiang ,  Miao-Wen Chen ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/428 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/1815

Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

Abstract translation: 提供一种多芯片封装结构，包括具有接地结构的基板; 两个半导体元件设置在基板上并与其电连接; 形成在所述基板上并封装半导体元件的密封剂，其中所述密封剂具有形成在所述半导体元件之间的多个圆形孔; 以及形成在每个圆孔中的电磁屏蔽结构，并连接到接地结构以实现电磁屏蔽效果。 还提供了一种用于形成多芯片封装的方法。

公开(公告)号：US20160181126A1

公开(公告)日：2016-06-23

申请号：US15054845

申请日：2016-02-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tai-Tsung Hsu ,  Cheng-Yu Chiang ,  Miao-Wen Chen ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L21/56 ,  H01L21/428 ,  H01L23/58 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L21/56 ,  H01L21/428 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/1815

Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

Abstract translation: 提供一种多芯片封装结构，包括具有接地结构的基板; 两个半导体元件设置在基板上并与其电连接; 形成在所述基板上并封装半导体元件的密封剂，其中所述密封剂具有形成在所述半导体元件之间的多个圆形孔; 以及形成在每个圆孔中的电磁屏蔽结构，并连接到接地结构以实现电磁屏蔽效果。 还提供了一种用于形成多芯片封装的方法。

公开(公告)号：US20150137337A1

公开(公告)日：2015-05-21

申请号：US14157904

申请日：2014-01-17

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Tsung-Tien Hsieh ,  Wen-Jung Chiang

IPC: H01L23/495 ,  H02B1/20 ,  H01L23/31

CPC classification number: H01L23/49555 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2924/00014

Abstract: A semiconductor package is disclosed, which includes: a die paddle portion; a plurality of conductive portions circumventing the die paddle portion; a power bus bar and a ground bus bar formed around the periphery of the die paddle portion; a semiconductor element attached to the die paddle portion and electrically connected to the conductive portions, the power bus bar, and the ground bus bar by a plurality of bonding wires; and an encapsulant encapsulating the semiconductor element and the bonding wires. The ground bus bar extends outward along the power bus bar and is mutually configured with the power bus bar so as to reduce the loop inductance and resistance of the power bus bar while in use.

Abstract translation: 公开了一种半导体封装，其包括：管芯焊盘部分; 围绕所述管芯片部分的多个导电部分; 电源母线和形成在所述芯片桨部的周边周围的接地母线; 半导体元件，其附接到所述管芯焊盘部分并且通过多个接合线电连接到所述导电部分，所述电力母线和所述接地母线; 以及封装半导体元件和接合线的密封剂。 接地母线沿着电源母线向外延伸，并与电源母线相互配置，以便在使用时降低电源母线的回路电感和电阻。

公开(公告)号：US20140225241A1

公开(公告)日：2014-08-14

申请号：US13922904

申请日：2013-06-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Yu Chiang ,  Wen-Jung Chiang ,  Hsing-Hung Lee

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49589 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00

Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.

Abstract translation: 公开了一种封装结构，其包括：具有形成在其下侧并填充有电介质材料的凹部的载体; 半导体元件，其设置在所述载体的上侧并电连接到所述载体; 以及密封剂，其形成在用于封装半导体元件的载体的上侧。 其中，电介质材料从密封剂暴露出来。 因此，当载体设置在电路板上时，电介质材料夹在载体的下侧和电路板之间以形成去耦电容器，从而提高电力完整性。

公开(公告)号：US09887102B2

公开(公告)日：2018-02-06

申请号：US15054845

申请日：2016-02-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tai-Tsung Hsu ,  Cheng-Yu Chiang ,  Miao-Wen Chen ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L21/56 ,  H01L23/36 ,  H01L23/552 ,  H01L23/31 ,  H01L21/428 ,  H01L23/367 ,  H01L23/58 ,  H01L25/065

CPC classification number: H01L21/56 ,  H01L21/428 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/1815

Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

公开(公告)号：US20130277858A1

公开(公告)日：2013-10-24

申请号：US13628620

申请日：2012-09-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tse-Shih Sung ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5225 ,  H01L23/64 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: An electrical interconnection structure includes: a signal transmission structure having a first through silicon via (TSV) and signal circuits connected to two opposite ends of the first TSV, respectively; and a grounding structure having a second TSV and grounding layers connected to two opposite ends of the second TSV, respectively. The grounding layers surround the signal circuits along the pathways thereof such that the ends of the first TSV are surrounded by the grounding layers with gaps therebetween. By changing the gaps between the grounding layers and the ends of the first TSV, the capacitance between the grounding layers and the signal circuits is adjusted so as to regulate the impedance therebetween.

Abstract translation: 电互连结构包括：信号传输结构，其具有分别连接到第一TSV的两个相对端的第一穿通硅通孔（TSV）和信号电路; 以及具有分别连接到第二TSV的两个相对端的第二TSV和接地层的接地结构。 接地层沿其路径围绕信号电路，使得第一TSV的端部被接地层包围，其间具有间隙。 通过改变接地层和第一TSV的端部之间的间隙，调整接地层和信号电路之间的电容，以便调节它们之间的阻抗。

公开(公告)号：US20140021591A1

公开(公告)日：2014-01-23

申请号：US13728112

申请日：2012-12-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Tse-Shih Sung ,  Wen-Jung Chiang ,  Hsin-Hung Lee

IPC: H01L23/60

CPC classification number: H01L23/60 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Abstract translation: 提供一种半导体元件，包括：具有形成在其中的多个第一导电通孔和第二导电通孔的基板; 形成在所述基板上并具有电连接到所述第一导电通孔的多个导电焊盘的再分布层; 以及形成在再分布层上并电连接到第二导电通孔的金属层。 金属层还具有多个开口，用于再分配层的导电焊盘从开口暴露而不电连接第一金属层。 因此，金属层和第二导电贯通孔形成能够防止电磁波进入或离开半导体元件的再分布层或侧面的屏蔽结构，从而有效地屏蔽电磁干扰。