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    Multi-bit deskewing of bus signals using a training pattern
    1.
    发明授权
    Multi-bit deskewing of bus signals using a training pattern 失效
    使用训练模式对总线信号进行多位歪斜校正

    公开(公告)号：US07036037B1

    公开(公告)日：2006-04-25

    申请号：US10218239

    申请日：2002-08-13

    申请人： Somnath Paul ,  Rakesh Mehrotra

    发明人： Somnath Paul ,  Rakesh Mehrotra

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12 ,  G06F13/423

    摘要： A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.

    摘要翻译： 公开了一种用于并行总线信号的多位去偏移的方法。 该方法包括接收包括多位字和训练模式的数据。 在检测到训练模式的第一控制字之后，计算对并行总线的每个位线中的多位数据字的每个数据位进行去偏移所需的位数。 将并行总线的每个位线中的多位数据字的每个数据位的去偏移所需的位数发送到位延迟线。 然后，系统输出去偏斜的数据字。

    Multiple byte data path encoding/decoding device and method
    4.
    发明授权
    Multiple byte data path encoding/decoding device and method 有权
    多字节数据路径编码/解码装置及方法

    公开(公告)号：US07138930B1

    公开(公告)日：2006-11-21

    申请号：US10937138

    申请日：2004-09-09

    申请人： Somnath Paul ,  Hamid Khodabandehlou

    发明人： Somnath Paul ,  Hamid Khodabandehlou

    IPC分类号： H03M7/00

    CPC分类号： H03M5/145 ,  H04L25/14 ,  H04L25/4906

    摘要： Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.

    摘要翻译： 用于执行编码和/或解码的系统和方法可以包括输入数据路径，其接收具有相对于彼此的顺序（重要性）的多个输入数据值。 每个输入数据值可以应用于多个计算路径（106-1至106-N），每个计算路径可以基于不同的预定差异值预先计算多个输出值。 多路复用器（114-1至114-N）可以根据与先前输入数据值相对应的视差值输出一个预计算的输出值。

    Techniques for Resilient Communication
    6.
    发明申请
    Techniques for Resilient Communication 有权
    弹性通信技术

    公开(公告)号：US20140095953A1

    公开(公告)日：2014-04-03

    申请号：US13631937

    申请日：2012-09-29

    申请人： Somnath Paul ,  Sriram R. Vangal ,  Michael D. Abbott ,  Eugene M. Kishinevsky

    发明人： Somnath Paul ,  Sriram R. Vangal ,  Michael D. Abbott ,  Eugene M. Kishinevsky

    IPC分类号： G06F11/14

    CPC分类号： G06F11/1443 ,  H04L1/20 ,  H04L1/242

    摘要： Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

    摘要翻译： 弹性沟通技巧。 数据路径存储要通过链接发送到接收节点的数据。 输出级耦合在数据路径和链路之间。 输出级包括双重采样机制，以保留通过链路传送到接收节点的数据副本。 错误检测电路与输出级耦合以检测数据通路或输出级中的瞬态定时误差。 响应于检测到错误，错误检测电路使得​​输出级发送通过链路发送的数据的副本。

    Logic for generating multicast/unicast address (es)
    7.
    发明授权
    Logic for generating multicast/unicast address (es) 有权
    用于生成多播/单播地址的逻辑

    公开(公告)号：US07016349B1

    公开(公告)日：2006-03-21

    申请号：US09676706

    申请日：2000-09-29

    申请人： S. Babar Raza ,  Somnath Paul

    发明人： S. Babar Raza ,  Somnath Paul

    IPC分类号： H04L12/56 ,  G06F12/00

    CPC分类号： H04L49/901 ,  H04L49/90

    摘要： An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the extraction and the skipping of the extraction.

    摘要翻译： 一种被配置为提取带内信息或者跳过带内信息的提取并执行预览操作的装置。 该装置可以被配置为在提取和提取的跳过之间切换。

    Low-latency DMA handling in pipelined processors
    8.
    发明授权
    Low-latency DMA handling in pipelined processors 有权
    流水线处理器中的低延迟DMA处理

    公开(公告)号：US06704863B1

    公开(公告)日：2004-03-09

    申请号：US09594219

    申请日：2000-06-14

    申请人： Somnath Paul ,  Gregory H. Efland

    发明人： Somnath Paul ,  Gregory H. Efland

    IPC分类号： G06F938

    CPC分类号： G06F9/3861 ,  G06F9/3802 ,  G06F9/3867

    摘要： A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids emptying and refilling the processor's instruction pipeline in order to service an interrupt request. Instead, a short sequence of instructions comprising the interrupt response is inserted into the pipeline. Normal pipeline operation stalls while the inserted instructions execute, but since flow is not disrupted the loss in bandwidth is not as great as if the pipeline were flushed. Furthermore, direct insertion of the instructions into the pipeline avoids the need for the processor to save its context and branch to an interrupt service routine in memory; this results in much faster response in servicing the interrupt, thereby reducing latency. In the preferred embodiment, the method applies to a pipelined processor having a RISC (Reduced Instruction Set Computer) architecture, which receives interrupt requests from one or more DMA memory controllers. The instructions inserted into the pipeline compute block address information for a DMA transfer. A system and processor implementing the method are disclosed, based on an enhancement of a conventional RISC processor design, and making use of registers and other existing logic resources within the processor. It is shown that the enhanced processor can respond to DMA interrupts with shorter latency and a smaller reduction in processor bandwidth than if conventional interrupt handling were used.

    摘要翻译： 提供了一种方法，系统和处理器，用于在响应中断时最小化流水线处理器中的处理器带宽的延迟和丢失。 该方法有利地避免了排空和重新填充处理器的指令流水线以便服务于中断请求。 相反，将包含中断响应的简短指令序列插入流水线。 正常的流水线操作在插入的指令执行时停止，但是由于流量不会中断，带宽的损失不如管道被冲洗的那么大。 此外，将指令直接插入到管线中避免了处理器将其上下文和分支保存到存储器中的中断服务程序的需要; 这导致在服务中断时响应更快，从而减少了延迟。 在优选实施例中，该方法适用于具有从一个或多个DMA存储器控制器接收中断请求的RISC（精简指令集计算机）架构的流水线处理器。 插入流水线的指令可计算DMA传输的块地址信息。 基于常规RISC处理器设计的增强以及利用处理器内的寄存器和其他现有逻辑资源，公开了实现该方法的系统和处理器。 显示出增强型处理器可以以较短的延迟响应DMA中断，并且比使用常规中断处理更小的处理器带宽减少。

    Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead
    9.
    发明授权
    Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead 有权
    用于存储和提取与单个存储器中存储的带内多播端口信息一起存储而不具有存储器读取周期开销的方法和逻辑

    公开(公告)号：US06578118B1

    公开(公告)日：2003-06-10

    申请号：US09676171

    申请日：2000-09-29

    申请人： S. Babar Raza ,  Somnath Paul

    发明人： S. Babar Raza ,  Somnath Paul

    IPC分类号： G06F1200

    CPC分类号： G06F5/10 ,  G06F5/065

    摘要： A method for writing and reading in-band information to and from a single storage element, comprising the steps of (A) receiving the in-band information, (B) storing data in either (i) a port information register when in a first state or (ii) a memory element when in a second state and (C) storing subsequent data in the memory element. The first state and the second state may be dependent upon a block position of the in-band information.

    摘要翻译： 一种用于向单个存储元件写入和读取带内信息的方法，包括以下步骤：（A）接收带内信息，（B）在（i）端口信息寄存器中存储数据的步骤 状态或（ii）处于第二状态的存储元件，（C）将后续数据存储在存储元件中。 第一状态和第二状态可以取决于带内信息的块位置。