公开(公告)号：US07494938B2

公开(公告)日：2009-02-24

申请号：US11671022

申请日：2007-02-05

申请人： Son V. Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

发明人： Son V. Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 提供了键合相互作用，更多的碳作为甲基端基和比现有技术的SiCOH电介质少的亚甲基-CH 2 - 交联基团。 SiCOH电介质的特征在于具有包含小于约1.40的CH 3 + CH 2拉伸的峰面积，小于约0.20的SiH拉伸的峰面积，大于约2.0的SiCH 3键合的峰面积以及大于约2.0的峰面积的FTIR光谱，以及 Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

公开(公告)号：US07202564B2

公开(公告)日：2007-04-10

申请号：US10906370

申请日：2005-02-16

申请人： Son Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

发明人： Son Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

IPC分类号： H01L23/48

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3/3 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：US20060183345A1

公开(公告)日：2006-08-17

申请号：US10906370

申请日：2005-02-16

申请人： Son Nguyen ,  Sarah Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl Restaino ,  Takeshi Nogami

发明人： Son Nguyen ,  Sarah Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl Restaino ,  Takeshi Nogami

IPC分类号： H01L21/31

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有包含小于约1.40的CH 3 N 2 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：US20070128882A1

公开(公告)日：2007-06-07

申请号：US11671022

申请日：2007-02-05

申请人： Son Nguyen ,  Sarah Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl Restaino ,  Takeshi Nogami

发明人： Son Nguyen ,  Sarah Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl Restaino ,  Takeshi Nogami

IPC分类号： H01L21/31

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3/3 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：US08399350B2

公开(公告)日：2013-03-19

申请号：US12700792

申请日：2010-02-05

申请人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L24/80 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

摘要： Method for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer, and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask exposes a surface of only the second portion of the cap layer which has the greater height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer. Material can be removed from the dielectric layer where exposed to the etchant.

摘要翻译： 一种在其电介质层中具有气隙的微电子元件的制造方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并延伸第二高度 高于介电层表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模仅暴露具有较大高度的盖层的第二部分的表面。 随后，蚀刻剂可以被引导到盖层的第一和第二部分。 材料可以从暴露于蚀刻剂的介电层去除。

公开(公告)号：US20110193230A1

公开(公告)日：2011-08-11

申请号：US12700792

申请日：2010-02-05

申请人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L24/80 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.

摘要翻译： 提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度 电介质层的表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模可以具有多个随机布置的孔。 每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。 掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。 随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。 可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。 此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。

公开(公告)号：US07422975B2

公开(公告)日：2008-09-09

申请号：US11206361

申请日：2005-08-18

申请人： Takeshi Nogami ,  Kensaku Ida

发明人： Takeshi Nogami ,  Kensaku Ida

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/7682

摘要： A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.

摘要翻译： 提供了一种制造用于形成在衬底上的微电子器件的层间电介质的方法。 该方法开始于在衬底层上形成第一和第二间隔层。 间隔层由牺牲电介质材料形成。 接下来，第一和第二电介质层分别形成在第一和第二间隔层上，使得第一和第二电介质层中的每一个被间隔层中的一个隔开。 第一和第二介电层各自包括第一和第二介电部件。 第二介电部件是牺牲绝缘材料。 去除第二电介质部件的至少一部分，从而在第一和第二电介质层中形成空隙。 第一和第二间隔层中的牺牲介电材料的至少一部分也被去除，从而在第一和/或第二间隔层中形成空隙。

公开(公告)号：US20070042589A1

公开(公告)日：2007-02-22

申请号：US11206361

申请日：2005-08-18

申请人： Takeshi Nogami ,  Kensaku Ida

发明人： Takeshi Nogami ,  Kensaku Ida

IPC分类号： H01L21/44

CPC分类号： H01L21/7682

摘要： A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.

摘要翻译： 提供了一种制造用于形成在衬底上的微电子器件的层间电介质的方法。 该方法开始于在衬底层上形成第一和第二间隔层。 间隔层由牺牲电介质材料形成。 接下来，第一和第二电介质层分别形成在第一和第二间隔层上，使得第一和第二电介质层中的每一个被间隔层中的一个隔开。 第一和第二介电层各自包括第一和第二介电部件。 第二介电部件是牺牲绝缘材料。 去除第二电介质部件的至少一部分，从而在第一和第二电介质层中形成空隙。 第一和第二间隔层中的牺牲介电材料的至少一部分也被去除，从而在第一和/或第二间隔层中形成空隙。

公开(公告)号：US08969197B2

公开(公告)日：2015-03-03

申请号：US13475526

申请日：2012-05-18

申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

IPC分类号： H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/76 ,  H01L24/82 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

摘要翻译： 具有改进的电迁移阻力的结构及其制造方法。 具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。 双层帽包括底部金属部分和顶部金属氧化物部分。 优选地，金属氧化物部分是MnO或MnSiO，金属部分是Mn或CuMn。 通过用杂质（在优选实施例中为Mn）掺杂互连，然后在互连的顶部处产生晶格缺陷来产生该结构。 这些缺陷驱使增加的杂质向互连顶表面迁移。 当形成电介质盖层时，一部分与分离的杂质反应，从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理，离子注入，压缩薄膜或其他方式产生。

公开(公告)号：US08841212B2

公开(公告)日：2014-09-23

申请号：US13609668

申请日：2012-09-11

申请人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.

摘要翻译： 一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。 该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。 接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。 在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。 在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。