公开(公告)号：US07494938B2

公开(公告)日：2009-02-24

申请号：US11671022

申请日：2007-02-05

申请人： Son V. Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

发明人： Son V. Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 提供了键合相互作用，更多的碳作为甲基端基和比现有技术的SiCOH电介质少的亚甲基-CH 2 - 交联基团。 SiCOH电介质的特征在于具有包含小于约1.40的CH 3 + CH 2拉伸的峰面积，小于约0.20的SiH拉伸的峰面积，大于约2.0的SiCH 3键合的峰面积以及大于约2.0的峰面积的FTIR光谱，以及 Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

公开(公告)号：US07202564B2

公开(公告)日：2007-04-10

申请号：US10906370

申请日：2005-02-16

申请人： Son Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

发明人： Son Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

IPC分类号： H01L23/48

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3/3 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：US07998880B2

公开(公告)日：2011-08-16

申请号：US11830425

申请日：2007-07-30

申请人： Son V. Nguyen ,  Sarah L. Lane ,  Eric G. Liniger ,  Kensaku Ida ,  Darryl D. Restaino

发明人： Son V. Nguyen ,  Sarah L. Lane ,  Eric G. Liniger ,  Kensaku Ida ,  Darryl D. Restaino

IPC分类号： H01L21/76

CPC分类号： H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

摘要翻译： 具有约3.0或更小的有效介电常数k的低k电介质堆叠，其中通过将至少一个纳米层引入电介质叠层来提高堆叠的机械性能。 在不显着增加叠层内的膜的介电常数并且不需要使本发明的电介质叠层进行任何后处理步骤的情况下，实现机械性能的改善。 具体地，本发明提供了一种低k电介质堆叠，其包含至少一个低k​​电介质材料和存在于至少一个低k​​电介质材料内的至少一个纳米层。

公开(公告)号：US20100028695A1

公开(公告)日：2010-02-04

申请号：US11830425

申请日：2007-07-30

申请人： Son V. Nguyen ,  Sarah L. Lane ,  Eric G. Liniger ,  Kensaku Ida ,  Darryl D. Restaino

发明人： Son V. Nguyen ,  Sarah L. Lane ,  Eric G. Liniger ,  Kensaku Ida ,  Darryl D. Restaino

IPC分类号： B32B15/04 ,  H05H1/24

CPC分类号： H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

摘要翻译： 具有约3.0或更小的有效介电常数k的低k电介质堆叠，其中通过将至少一个纳米层引入电介质叠层来提高堆叠的机械性能。 在不显着增加叠层内的膜的介电常数并且不需要使本发明的电介质叠层进行任何后处理步骤的情况下，实现机械性能的改善。 具体地，本发明提供了一种低k电介质堆叠，其包含至少一个低k​​电介质材料和存在于至少一个低k​​电介质材料内的至少一个纳米层。

公开(公告)号：US07265437B2

公开(公告)日：2007-09-04

申请号：US10906815

申请日：2005-03-08

申请人： Son V. Nguyen ,  Sarah L. Lane ,  Eric G. Liniger ,  Kensaku Ida ,  Darryl D. Restaino

发明人： Son V. Nguyen ,  Sarah L. Lane ,  Eric G. Liniger ,  Kensaku Ida ,  Darryl D. Restaino

IPC分类号： H01L21/58

CPC分类号： H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

摘要翻译： 具有约3.0或更小的有效介电常数k的低k电介质堆叠，其中通过将至少一个纳米层引入电介质叠层来提高堆叠的机械性能。 在不显着增加叠层内的膜的介电常数并且不需要使本发明的电介质叠层进行任何后处理步骤的情况下，实现机械性能的改善。 具体地，本发明提供了一种低k电介质堆叠，其包含至少一个低k​​电介质材料和存在于至少一个低k​​电介质材料内的至少一个纳米层。

公开(公告)号：US06939797B2

公开(公告)日：2005-09-06

申请号：US10706773

申请日：2003-11-12

申请人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

发明人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

IPC分类号： H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/461

CPC分类号： H01L21/76834 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

摘要翻译： 公开了一种先进的后端（BEOL）金属化结构。 该结构包括具有低介电常数（低-k）的扩散阻挡层或覆盖层，其中通过等离子体增强化学气相沉积（PE CVD）工艺，覆盖层由氮化硅形成。 金属化结构还包括由具有小于约4的介电常数的含碳电介质材料形成的层间电介质（ILD），以及优选由氮化硅或碳化硅形成的ILD上的连续硬掩模层。 还公开了一种用于形成BEOL金属化结构的方法。 该方法包括预清洁或预激活步骤，以改善盖层与下面的铜导体的粘合性。 预清洁或预活化步骤包括将铜表面暴露于包括氢，氨，氮和/或惰性气体的还原等离子体。

公开(公告)号：US06737747B2

公开(公告)日：2004-05-18

申请号：US10047965

申请日：2002-01-15

申请人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

发明人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

公开(公告)号：US20080130200A1

公开(公告)日：2008-06-05

申请号：US12034728

申请日：2008-02-21

申请人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

IPC分类号： H01G4/38

CPC分类号： H01L23/5223 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

摘要翻译： 本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。 本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

公开(公告)号：US08120143B2

公开(公告)日：2012-02-21

申请号：US12034728

申请日：2008-02-21

申请人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

摘要翻译： 本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。 本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

公开(公告)号：US07585722B2

公开(公告)日：2009-09-08

申请号：US11306746

申请日：2006-01-10

申请人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

摘要翻译： 本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。 本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。