公开(公告)号：US08779600B2

公开(公告)日：2014-07-15

申请号：US13344009

申请日：2012-01-05

申请人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Satyanarayana V. Nitta

发明人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Satyanarayana V. Nitta

IPC分类号： H01L29/40

CPC分类号： H01L23/5384 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249969 ,  H01L2924/00

摘要： A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

摘要翻译： 一种电介质堆叠和使用单步沉积工艺将叠层沉积到衬底的方法。 电介质堆叠包括具有不同组成原子百分比，密度和孔隙率的相同元素化合物的致密层和多孔层。 该堆叠增强机械模量强度并增强氧化和铜扩散阻挡性能。 电介质叠层在整个网络中具有无机或杂化的无机 - 有机随机三维共价键，其含有不同化学组成的不同区域，例如与相同类型材料的低k组分相邻但具有较高孔隙率的盖组分 。

公开(公告)号：US20130175697A1

公开(公告)日：2013-07-11

申请号：US13344009

申请日：2012-01-05

申请人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Satyanarayana V. Nitta

发明人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Satyanarayana V. Nitta

IPC分类号： H01L23/538 ,  H01L21/31 ,  B32B9/04

CPC分类号： H01L23/5384 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249969 ,  H01L2924/00

摘要： A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

摘要翻译： 一种电介质堆叠和使用单步沉积工艺将叠层沉积到衬底的方法。 电介质堆叠包括具有不同组成原子百分比，密度和孔隙率的相同元素化合物的致密层和多孔层。 该堆叠增强机械模量强度并增强氧化和铜扩散阻挡性能。 电介质叠层在整个网络中具有无机或杂化的无机 - 有机随机三维共价键，其含有不同化学组成的不同区域，例如与相同类型材料的低k组分相邻但具有较高孔隙率的盖组分 。

公开(公告)号：US07749892B2

公开(公告)日：2010-07-06

申请号：US11564358

申请日：2006-11-29

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

摘要翻译： 提供的互连，其包括具有顶表面和下表面的铜导体，其中帽形成在金属导体的顶表面上。 盖由双层叠或多层薄膜形成，层压膜包括超紫（UV）阻挡膜和扩散阻挡膜。 扩散阻挡膜和UV阻挡膜可以通过中间膜分离。

公开(公告)号：US20080122103A1

公开(公告)日：2008-05-29

申请号：US11564358

申请日：2006-11-29

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

摘要翻译： 提供的互连，其包括具有顶表面和下表面的铜导体，其中帽形成在金属导体的顶表面上。 盖由双层叠或多层薄膜形成，层压膜包括超紫（UV）阻挡膜和扩散阻挡膜。 扩散阻挡膜和UV阻挡膜可以通过中间膜分离。

公开(公告)号：US20070249156A1

公开(公告)日：2007-10-25

申请号：US11672608

申请日：2007-02-08

申请人： Griselda Bonilla ,  Stephen M. Gates ,  Shom Ponoth ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

发明人： Griselda Bonilla ,  Stephen M. Gates ,  Shom Ponoth ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

IPC分类号： H01L21/4763

CPC分类号： H01L21/76826 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76883

摘要： A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an etch stop and barrier layer. In situ reaction of the damaged regions with a suitable silylation agent just prior to a passivation barrier cap deposition is proposed as the most efficacious means to repair all the damage sustained by the dielectric. Variations of this method which include ex situ rather than in situ silylation are also described for use with hard mask free integration with selective barrier caps.

摘要翻译： 描述了一种用于修复由低k有机硅酸盐电介质持续的过程诱导的损伤作为反应离子蚀刻，抗蚀剂条，湿清洁和CMP操作在将这些电介质纳入包含电介质的微电子互连结构的硬掩模中的CMP操作的方法 盖是蚀刻停止层和阻挡层。 在钝化阻挡层沉积之前，损伤区域与合适的甲硅烷基化剂的原位反应被提出作为修复由电介质所承受的所有损伤的最有效手段。 还描述了包括异位原位甲硅烷基化的这种方法的变化，用于与选择性屏障帽的硬掩模自由积分。

公开(公告)号：US20120068344A1

公开(公告)日：2012-03-22

申请号：US12887010

申请日：2010-09-21

申请人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。

公开(公告)号：US20090140428A1

公开(公告)日：2009-06-04

申请号：US11949189

申请日：2007-12-03

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。

公开(公告)号：US08809183B2

公开(公告)日：2014-08-19

申请号：US12887010

申请日：2010-09-21

申请人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。

公开(公告)号：US20110092067A1

公开(公告)日：2011-04-21

申请号：US12972808

申请日：2010-12-20

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。

公开(公告)号：US07884477B2

公开(公告)日：2011-02-08

申请号：US11949189

申请日：2007-12-03

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。