公开(公告)号：US5278795A

公开(公告)日：1994-01-11

申请号：US47334

申请日：1990-08-16

Applicant: Stephane Barbu ,  Guy Imbert

Inventor： Stephane Barbu ,  Guy Imbert

IPC: G11C8/08 ,  G11C7/00

CPC classification number: G11C8/08

Abstract: The invention relates to a memory having a line decoder provided with a Darlington-type switching stage. When the deselection time T.sub.1 of a line is notably shorter than the intrinsic switching time T.sub.3 of a memory cell (M11 . . . Mnp), a discharge current I.sub.D is temporarily applied to the lower line conductor (1' . . . n') of the line (L1 . . . Ln) which is deselected. To achieve this, the current source I.sub.D is connected to said lower line conductors (1' . . . n') via delay circuits (RL1, DL1 . . . RLn, DLn) having a time constant T.sub.2 which is smaller than T.sub.3 and at least equal to T.sub.1.

Abstract translation: 本发明涉及具有达林顿型切换台的线路解码器的存储器。 当线的取消选择时间T1明显短于存储单元（M11 ... Mnp）的固有切换时间T3时，暂时将放电电流ID施加到下线导体（1'... n'）， 的线路（L1 ... Ln）被取消选择。 为了实现这一点，电流源ID通过具有小于T3的时间常数T2的延迟电路（RL1，DL1 ... RLn，DLn）连接到所述下线导体（1'... n'），并且在 最小等于T1。

公开(公告)号：US5185582A

公开(公告)日：1993-02-09

申请号：US874256

申请日：1992-04-24

Applicant: Stephane Barbu

Inventor： Stephane Barbu

IPC: H03F1/32 ,  H03F3/45

CPC classification number: H03F3/4521 ,  H03F1/3211 ,  H03F3/45089 ,  H03F2200/516 ,  H03F2203/45024 ,  H03F2203/45026 ,  H03F2203/45202 ,  H03F2203/45352 ,  H03F2203/45371 ,  H03F2203/45374 ,  H03F2203/45702

Abstract: A differential amplifier stage including a main pair of transistors (T1, T2) having their bases connected to a pair of input terminals (V1, V2) and their collectors coupled to a supply terminal (Vcc) via respective cascode connected transistors (T5, T6). The emitters are interconnected to a current source. An auxiliary pair of transistors (T3T4), have their bases connected to the pair of input terminals, their collectors coupled to a supply voltage (VCC'), and their emitters interconnected to a current source. A summation device supplies a part of the collector current from the auxiliary pair of transistors to the main pair of transistors. The summation device includes a first (R3, R5) and a second (R4, R6) resistor bridge coupled between the collectors of the main pair of transistors and the supply voltage (Vcc') with respective taps on the first and the second resistor bridge coupled to respective collectors for the auxiliary pair of transistors.

Abstract translation: 一种差分放大器级，包括主要的一对晶体管（T1，T2），其基极连接到一对输入端子（V1，V2），并且它们的集电极通过相应的共源共栅连接的晶体管（T5，T6）耦合到电源端子（Vcc） ）。 发射器互连到电流源。 一对辅助晶体管（T3 + L，T4）的基极连接到该对输入端子，它们的集电极耦合到电源电压（VCC'），并且它们的发射极互连到电流源。 求和装置将集电极电流的一部分从辅助晶体管对提供给主对晶体管。 所述求和装置包括耦合在主对晶体管的集电极之间的第一（R3，R5）和第二（R4，R6）电阻器电阻，以及在第一和第二电阻器桥上的各个抽头的电源电压（Vcc'） 耦合到用于辅助晶体管对的各个集电极。

公开(公告)号：US5063312A

公开(公告)日：1991-11-05

申请号：US618778

申请日：1990-11-27

Applicant: Stephane Barbu ,  Laurent Le Pailleur

Inventor： Stephane Barbu ,  Laurent Le Pailleur

IPC: H03K3/0233 ,  H03K3/2897 ,  H03K5/00 ,  H03K5/08 ,  H03K5/13

CPC classification number: H03K3/2897 ,  H03K3/02337 ,  H03K5/086 ,  H03K5/133 ,  H03K2005/00176 ,  H03K2005/00228

Abstract: A delay circuit with adjustable delay employs a switching flip-flop which includes a differential amplifier (A) having two outputs each one feedback-looped respectively onto two inputs, so as to produce the said switching. The looping is produced by a first (AD1) and a second (AD2) adder, each having a first, a second and a third input. The first inputs are connected to corresponding outputs of the differential amplifier to produce the feedback looping. The second inputs are intended to be connected respectively to a first and a second terminal delivering a signal to be delayed (V.sub.1.sup.+, V.sub.1.sup.-) and the third inputs receive respectively a first and a second control voltage (V.sub.3.sup.+, V.sub.3.sup.-). The delay is a function of the difference between the first and the second control voltage. The outputs of the adders are connected respectively to corresponding inputs of the differential amplifier.

Abstract translation: 具有可调节延迟的延迟电路采用开关触发器，其包括具有两个输出的差分放大器（A），每个输出分别反馈回到两个输入端，以产生所述切换。 循环由第一（AD1）和第二（AD2）加法器产生，每个具有第一，第二和第三输入。 第一个输入端连接到差分放大器的相应输出端，产生反馈回路。 第二输入端分别连接到传送待延迟信号（V1 +，V1-）的第一和第二端子，第三输入端分别接收第一和第二控制电压（V3 +，V3-）。 延迟是第一和第二控制电压之差的函数。 加法器的输出分别连接到差分放大器的相应输入端。

公开(公告)号：US5329279A

公开(公告)日：1994-07-12

申请号：US947665

申请日：1992-09-18

Applicant: Stephane Barbu ,  Laurent LePailleur

Inventor： Stephane Barbu ,  Laurent LePailleur

IPC: H03M7/00 ,  H03M1/36 ,  H03M7/02 ,  H03M7/08 ,  H03M7/16 ,  H03M7/14

CPC classification number: H03M7/165 ,  H03M7/16

Abstract: A method of transcoding digital data which, at the start, appear in the form of a thermometric code, the successive values of which may be represented by a first bit matrix (columns 1 to 8). The method uses an intermediate code defined by a second matrix (low significance), (columns (1), (2), (3) and (4)), and by a third matrix (high significance), (columns 4 and 8), which is extracted from the first matrix. The intermediate code delivers digital words which are shorter than the starting words and permits a later transformation into a binary code (columns [1], [2], [3], [4],) which is very simple. A decoder and a converter using this method is described where the decoder is organized so as to first produce the values of the intermediate code and then, the corresponding values in binary code. The converter employs analog gates with multiple inputs instead of the purely logic input blocks of the decoder.

Abstract translation: 数字数据的代码转换方法，其开始以温度测量代码的形式出现，其连续值可以由第一位矩阵（列1至8）表示。 该方法使用由第二矩阵（低意义），（列（1），（2），（3）和（4））定义的中间码，以及由第三矩阵（高重要性），（列4和8） ），其从第一矩阵提取。 中间代码提供比起始字短的数字字，并允许稍后的变换成二进制代码（列[1]，[2]，[3]，[4]），这是非常简单的。 描述了使用该方法的解码器和转换器，其中解码器被组织以便首先产生中间代码的值，然后产生二进制代码中的相应值。 转换器采用具有多个输入的模拟门，而不是解码器的纯逻辑输入块。

公开(公告)号：US5079497A

公开(公告)日：1992-01-07

申请号：US567415

申请日：1990-08-14

Applicant: Stephane Barbu ,  Richard Morisson ,  Philippe Gandy

Inventor： Stephane Barbu ,  Richard Morisson ,  Philippe Gandy

IPC: G05F1/56 ,  G05F1/565

CPC classification number: G05F1/565 ,  Y10S323/901

Abstract: The invention relates to a circuit intended to supply a reference voltage comprising a voltage generator (REF) provided with a supply terminal and an output for supplying a voltage having a given nominal value (V.sub.R) and comprising a differential amplifier (A), fed by a first supply voltage, whose non-inverting input is connected to the output of the voltage generator (REF). An output of the differential amplifier (A) is connected to an input of a follower stage (T) through a controlled switching device (1), the follower stage (T) having its input connected to the first supply voltage through a first resistor (R.sub.1) and having its output, which supplies the said reference voltage (V.sub.D), connected on the one hand to the inverting input of the differential amplifier (A) through a divider bridge and on the other hand to the supply termianl of the voltage generator (REF). A control circuit (C) of the switching device is operated so as to receive at least the supply voltage in such a manner that the switching device (1) is closed when the supply voltage reaches a threshold for which both the voltage generator and the differential amplifier are in a nominal operating zone.

Abstract translation: 本发明涉及一种旨在提供参考电压的电路，该电路包括设置有电源端子的电压发生器（REF）和用于提供具有给定额定值（VR）的电压并且包括差分放大器（A）的输出的输出，该差分放大器 第一电源电压，其非反相输入端连接到电压发生器（REF）的输出端。 差分放大器（A）的输出通过受控开关器件（1）连接到跟随器级（T）的输入端，所述跟随器级（T）的输入端通过第一电阻器 R1），并且其输出端通过分压桥将所述参考电压（VD）提供给差分放大器（A）的反相输入，另一方面连接到电压发生器的电源端 （REF）。 操作开关装置的控制电路（C），以便至少接收电源电压，使得当电源电压达到电压发生器和差动器的阈值时，开关装置（1）闭合 放大器处于标称工作区。

公开(公告)号：US5142245A

公开(公告)日：1992-08-25

申请号：US685267

申请日：1991-04-12

Applicant: Stephane Barbu

Inventor： Stephane Barbu

IPC: H03F3/30 ,  H03K17/66 ,  H03K19/00

CPC classification number: H03K19/001 ,  H03F3/3088 ,  H03K17/666

Abstract: A power-amplifier cell which comprises an inverting input amplifier made up of a first transistor (T.sub.1) having a collector connected to a first supply-voltage terminal via a first resistor (R.sub.11), and an output stage comprising a second (T.sub.4) and a third (T.sub.6) transistor whose collector-emitter paths are arranged in series. The common point between the second and third transistors forms an output (5) of the power amplifier. The second transistor (T.sub.4) has its base connected to the collector of the first transistor (T.sub.1) and a control signal is applied to the base of the third transistor (T.sub.6) via a second resistor (R.sub.16). Furthermore, a first capacitor (C.sub.1) is arranged in parallel with the first resistor (R.sub.11) and the control signal is the input signal (E) or a fraction thereof. The power amplifier may comprise two cells whose first transistors (T.sub.1) have their emitters coupled to one another.

Abstract translation: 一种功率放大器单元，包括由具有通过第一电阻器（R11）连接到第一电源电压端子的集电极的第一晶体管（T1）构成的反相输入放大器，以及包括第二（T4）和 其集电极 - 发射极路径串联布置的第三（T6）晶体管。 第二和第三晶体管之间的共同点形成功率放大器的输出（5）。 第二晶体管（T4）的基极连接到第一晶体管（T1）的集电极，并且经由第二电阻器（R16）将控制信号施加到第三晶体管（T6）的基极。 此外，第一电容器（C1）与第一电阻器（R11）并联布置，并且控制信号是输入信号（E）或其分数。 功率放大器可以包括两个单元，其第一晶体管（T1）的发射极彼此耦合。

公开(公告)号：US4972103A

公开(公告)日：1990-11-20

申请号：US387454

申请日：1989-07-28

Applicant: Stephane Barbu

Inventor： Stephane Barbu

IPC: H03K3/2897 ,  H03K3/2893 ,  H03K5/08 ,  H03K17/30 ,  H03K17/60

CPC classification number: H03K3/2893

Abstract: An accelerated switching input circuit includes an emitter coupled logic stage having two transistors. The first transistor receives at its base an input signal and the second transistor receives at its base a control signal generated from the signal at the collector of the first transistor. A third transistor (T.sub.6) has its base connected to the collector of the first transistor (T.sub.3). A first resistor (R.sub.10), a second resistor (R.sub.11) and a third resistor (R.sub.12) are disposed in series between the emitter of the third transistor and a reference voltage (U.sub.REF) source. The point B common to the resistors R.sub.11 and R.sub.12 is coupled to the base of the second transistor (T.sub.4).

Abstract translation: 加速开关输入电路包括具有两个晶体管的发射极耦合逻辑级。 第一晶体管在其基极处接收输入信号，并且第二晶体管在其基极处接收从第一晶体管的集电极处的信号产生的控制信号。 第三晶体管（T6）的基极连接到第一晶体管（T3）的集电极。 第一电阻器（R10），第二电阻器（R11）和第三电阻器（R12）串联布置在第三晶体管的发射极和参考电压（UREF）源之间。 电阻器R11和R12共用的点B耦合到第二晶体管（T4）的基极。

公开(公告)号：US4970452A

公开(公告)日：1990-11-13

申请号：US452852

申请日：1989-12-19

Applicant: Stephane Barbu ,  Richard Morisson

Inventor： Stephane Barbu ,  Richard Morisson

IPC: G05F3/22 ,  G05F1/56 ,  H03K17/66

CPC classification number: H03K17/667

Abstract: An integrated circuit comprising a current generator which is switchable to at least two modes. A first stage comprises a current mirror (T.sub.3, T.sub.4) having two branches. A differential pair second stage (T.sub.1, T.sub.2) is either in a balanced state (current output zero) or in an unbalanced state (current source R.sub.10, T.sub.10 supplying a current I.sub.1). In the balanced state a second current source (R.sub.20, T.sub.20) supplies a current which maintains the currents in the two branches of the current mirror constant.

Abstract translation: 一种集成电路，包括可切换至少两种模式的电流发生器。 第一级包括具有两个分支的电流镜（T3，T4）。 差分对第二级（T1，T2）处于平衡状态（电流输出为零）或不平衡状态（电流源R10，提供电流I1的T10）。 在平衡状态下，第二电流源（R20，T20）提供保持电流镜的两个分支中的电流恒定的电流。