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1.发明申请ENHANCED BONDING INTERFACES ON CARBON-BASED MATERIALS FOR NANOELECTRONIC DEVICES 审中-公开用于纳米电子设备的碳基材料的增强接合界面公开(公告)号：US20110233513A1
公开(公告)日：2011-09-29
申请号：US12748542
申请日：2010-03-29
申请人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Stephen M. Gates , Tuan A. Vo , Deborah A. Neumayer , Son Van Nguyen
发明人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Stephen M. Gates , Tuan A. Vo , Deborah A. Neumayer , Son Van Nguyen
CPC分类号： H01L29/1606 , H01L29/7781 , H01L29/78 , H01L29/7831
摘要： Semiconductor structures and electronic devices are provided that includes at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material.
摘要翻译： 提供半导体结构和电子器件，其包括位于碳基材料的上表面上的至少一层界面介电材料层。 所述至少一层界面介电材料具有与碳基材料相同的短程结晶结合结构，通常是六边形，因此至少一层界面介电材料不会改变 碳基材料的电子结构。 具有与碳基材料相同的短程结晶结合结构的至少一层界面介电材料的存在改善了碳基材料和任何覆盖材料层（包括介电材料）之间的界面结合， 导电材料或介电材料和导电材料的组合。 改进的界面结合又有助于形成包括碳基材料的装置。
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2.发明授权公开(公告)号：US07030468B2
公开(公告)日：2006-04-18
申请号：US10758724
申请日：2004-01-16
IPC分类号： H01L23/58
CPC分类号： H01L21/02126 , C23C16/401 , C23C16/56 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31633 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.
摘要翻译： 包含Si，C，O和H元素的介电材料具有机械性能（拉伸应力，弹性模量，硬度内聚强度，水中裂纹速度）的特定值，这导致稳定的超低k膜，其不被水蒸气降解 或集成处理。 电介质材料具有约2.8或更小的介电常数，小于45MPa的拉伸应力，约2至约15GPa的弹性模量和约0.2至约2GPa的硬度。 还提供了包括本发明的电介质材料的电子结构以及制造介电材料的各种方法。
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3.发明授权公开(公告)号：US07282458B2
公开(公告)日：2007-10-16
申请号：US11268106
申请日：2005-11-07
IPC分类号： H01L21/469
CPC分类号： H01L21/02126 , C23C16/401 , C23C16/56 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31633 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.
摘要翻译： 包含Si，C，O和H元素的介电材料具有机械性能（拉伸应力，弹性模量，硬度内聚强度，水中裂纹速度）的特定值，这导致稳定的超低k膜，其不被水蒸气降解 或集成处理。 电介质材料具有约2.8或更小的介电常数，小于45MPa的拉伸应力，约2至约15GPa的弹性模量和约0.2至约2GPa的硬度。 还提供了包括本发明的电介质材料的电子结构以及制造介电材料的各种方法。
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4.发明申请SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP 有权半导体芯片与基于图形的设备在芯片的互连结构中公开(公告)号：US20120205626A1
公开(公告)日：2012-08-16
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译： 半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。 该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。 所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。 所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。 第二电介质材料包括其中包含的至少一个第二导电区域，并且至少一个第二导电区域与至少一个含石墨烯的半导体器件的导电元件接触。
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5.发明授权Semiconductor chip with graphene based devices in an interconnect structure of the chip 有权半导体芯片采用基于石墨烯的器件，在芯片的互连结构中公开(公告)号：US08440999B2
公开(公告)日：2013-05-14
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
IPC分类号： H01L29/78
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译： 半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。 该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。 所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。 所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。 第二电介质材料包括其中包含的至少一个第二导电区域，并且所述至少一个第二导电区域与所述至少一个含石墨烯的半导体器件的导电元件接触。
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6.发明授权Reliable BEOL integration process with direct CMP of porous SiCOH dielectric 有权可靠的BEOL集成工艺与多孔SiCOH电介质的直接CMP公开(公告)号：US07948083B2
公开(公告)日：2011-05-24
申请号：US11763135
申请日：2007-06-14
IPC分类号： H01L29/40
CPC分类号： H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.
摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法至少包括化学机械抛光和UV曝光或化学修复处理的步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。
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7.发明授权Reliable BEOL integration process with direct CMP of porous SiCOH dielectric 失效可靠的BEOL集成工艺与多孔SiCOH电介质的直接CMP公开(公告)号：US07253105B2
公开(公告)日：2007-08-07
申请号：US11063152
申请日：2005-02-22
IPC分类号： H01L21/44
CPC分类号： H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.
摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。
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8.发明申请BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES 失效用于石墨设备的低等效氧化物厚度的双层栅介质公开(公告)号：US20130207080A1
公开(公告)日：2013-08-15
申请号：US13369901
申请日：2012-02-09
申请人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
发明人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L21/0237 , B82Y30/00 , B82Y40/00 , H01L21/02378 , H01L21/02527 , H01L21/02617 , H01L21/02661 , H01L29/1606 , H01L29/4908 , H01L29/513 , H01L29/66045 , H01L29/7781 , H01L29/78684
摘要： A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
摘要翻译： 在石墨烯层的最上表面上设置氮化硅层，然后在氮化硅层的最上表面上设置二氧化铪层。 氮化硅层用作二氧化铪层的润湿剂，从而防止在石墨烯层顶上形成不连续的二氧化铪塔。 共同形成低EOT双层栅极电介质的氮化硅层和二氧化铪层在石墨烯层的顶部呈现连续的形态。
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9.发明授权Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices 失效嵌入式纳米UV阻挡和扩散屏障，提高铜/超低K层间电介质电子器件的可靠性公开(公告)号：US07749892B2
公开(公告)日：2010-07-06
申请号：US11564358
申请日：2006-11-29
申请人： Griselda Bonilla , Christos D. Dimitrakopoulos , Son V. Nguyen , Alfred Grill , Satyanarayana V. Nitta , Darryl D. Restaino , Terry A. Spooner
发明人： Griselda Bonilla , Christos D. Dimitrakopoulos , Son V. Nguyen , Alfred Grill , Satyanarayana V. Nitta , Darryl D. Restaino , Terry A. Spooner
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76825 , H01L21/76832 , H01L21/76844 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.
摘要翻译： 提供的互连，其包括具有顶表面和下表面的铜导体，其中帽形成在金属导体的顶表面上。 盖由双层叠或多层薄膜形成，层压膜包括超紫（UV）阻挡膜和扩散阻挡膜。 扩散阻挡膜和UV阻挡膜可以通过中间膜分离。
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公开(公告)号：US20100052018A1
公开(公告)日：2010-03-04
申请号：US12198592
申请日：2008-08-26
IPC分类号： H01L21/768 , H01L29/78
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/28518 , H01L21/76885 , H01L23/481 , H01L29/665 , H01L29/78 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy can be derived from either a semiconductor nanowire or an epitaxial grown semiconductor material. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion. The lower portion of the continuous metal semiconductor alloy and the vertical pillar portion are not separated by a material interface. Instead, the two portions of the continuous metal semiconductor alloy are of unitary construction, i.e., a single piece.
摘要翻译： 公开了一种接触结构，其中连续的金属半导体合金位于包含在电介质材料内的通孔内。 连续半导体金属合金与位于连续半导体金属合金顶部的第一金属水平的上金属线和至少位于连续金属半导体合金下方的源极和漏极扩散区的表面直接接触。 连续金属半导体合金可以衍生自半导体纳米线或外延生长半导体材料。 连续金属半导体合金包括包含在每个源极和漏极区域的上表面内的下部以及从下部向上延伸的垂直柱部分。 连续金属半导体合金的下部和垂直支柱部分不被材料界面分离。 相反，连续金属半导体合金的两个部分是单一结构，即单件。
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