公开(公告)号：US20050170609A1

公开(公告)日：2005-08-04

申请号：US11050469

申请日：2005-02-03

申请人： Susan Alie ,  Bruce Wachtmann ,  Lawrence Felton ,  Changhan Yun

发明人： Susan Alie ,  Bruce Wachtmann ,  Lawrence Felton ,  Changhan Yun

IPC分类号： B81B7/00 ,  H01L21/30 ,  H01L21/46 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： B81C1/00301 ,  B81B7/0006 ,  B81B2203/0353 ,  B81B2207/093 ,  B81B2207/095 ,  B81C2203/019 ,  H01L21/76898 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05023 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/8182 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014

摘要： A conductive bond for through-wafer interconnect is produced by forming an electrode through a first wafer from a component on a front side of the first wafer to a back side of the first wafer, forming a first electrically conductive interface in contact with an exposed portion of the electrode on the back side of the first wafer, and conductively bonding the first electrically conductive interface with a second electrically conductive interface on a second wafer under pressure at a temperature below the thermal budget of the stacked wafer device. The process temperature is generally well below the melting points of the electrically conductive interfaces. In some embodiments, the conductive bonding may be facilitated or enabled by performing the conductive bonding in a vacuum.

摘要翻译： 通过从第一晶片的前侧的部件到第一晶片的后侧形成电极通过第一晶片形成电极，形成用于晶片间互连的导电接合，形成与暴露部分接触的第一导电界面 并且在低于所述堆叠晶片装置的热量预算的温度的压力下，在第二晶片上将所述第一导电界面与第二导电界面导电地接合。 工艺温度通常远低于导电界面的熔点。 在一些实施例中，可以通过在真空中执行导电接合来促进或实现导电接合。

公开(公告)号：US09008602B2

公开(公告)日：2015-04-14

申请号：US13464092

申请日：2012-05-04

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H04B1/06 ,  H04B1/44 ,  H03C7/02 ,  H01Q11/12 ,  H04M1/00 ,  H04B1/16 ,  H04B1/00 ,  H04B7/08

CPC分类号： H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

摘要翻译： 分集接收机交换机包括被配置为与收发机通信的至少一个第二级交换机。 分集接收机交换机还可以包括耦合在分集接收机天线和第二级交换机之间的至少一个第一级交换机。 第一级开关可以被配置为处理与第二级开关不同的功率量。 分集接收器开关可以包括被配置为与收发器通信的一组第二级交换机。 第一级开关可以被配置为处理比第二级开关组中的每个开关更多的功率。 或者，分集接收器开关包括耦合在分集接收器天线和第二级开关之间的一组第一级开关。 第二级开关可以被配置为处理比每个第一级开关更多的功率。

公开(公告)号：US08907450B2

公开(公告)日：2014-12-09

申请号：US13293075

申请日：2011-11-09

申请人： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

发明人： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

IPC分类号： H01L29/92 ,  H01L21/02 ,  H01G4/12 ,  H01G4/33 ,  H01L49/02

CPC分类号： H01L29/66174 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L28/75

摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

摘要翻译： 提供了用于高Q装置的金属半导体晶片接合的方法和装置。 示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。 在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。 重掺杂的非本征半导体层接触电介质层。 电介质和非本征半导体层夹在第一和第二板之间。 在第一板和电介质层之间形成金属间层。 金属间化合物层被热压接合到第一板和电介质层。 电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

公开(公告)号：US20130295866A1

公开(公告)日：2013-11-07

申请号：US13464092

申请日：2012-05-04

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H04B1/16

CPC分类号： H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

公开(公告)号：US20130222060A1

公开(公告)日：2013-08-29

申请号：US13406431

申请日：2012-02-27

申请人： Chi Shun Lo ,  Jonghae Kim ,  Wesley Nathaniel Allen ,  Chengjie Zuo ,  Changhan Yun ,  Thomas Andrew Myers ,  Prasad Srinivasa Siva Gudem ,  Matthew Michael Nowak

发明人： Chi Shun Lo ,  Jonghae Kim ,  Wesley Nathaniel Allen ,  Chengjie Zuo ,  Changhan Yun ,  Thomas Andrew Myers ,  Prasad Srinivasa Siva Gudem ,  Matthew Michael Nowak

IPC分类号： H03H7/38 ,  H03F1/00

CPC分类号： H03H7/38 ,  H03H7/09

摘要： An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.

摘要翻译： 公开了一种阻抗匹配电路。 阻抗匹配电路包括两个或更多个相互耦合的电感器。 阻抗匹配电路的总自感小于包括不相互耦合的电感器的对应阻抗匹配电路。 两个或更多个相互耦合的电感器可以具有与相应的阻抗匹配电路中的电流比匹配的已知电流比。

公开(公告)号：US20130120951A1

公开(公告)日：2013-05-16

申请号：US13356717

申请日：2012-01-24

申请人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H05K1/03 ,  H01L21/60 ,  H05K7/06 ,  H01L21/58

CPC分类号： H01L27/0688 ,  H01L2224/18

摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.

摘要翻译： 芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。 第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。 具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。 还有一种形成芯片组的方法。

公开(公告)号：US20130076209A1

公开(公告)日：2013-03-28

申请号：US13241356

申请日：2011-09-23

申请人： Chengjie Zuo ,  Chi Shun Lo ,  Sanghoon Joo ,  Changhan Yun ,  Jonghae Kim

发明人： Chengjie Zuo ,  Chi Shun Lo ,  Sanghoon Joo ,  Changhan Yun ,  Jonghae Kim

IPC分类号： H01L41/107 ,  H01L41/04 ,  H01L41/047

CPC分类号： H03H9/02157 ,  H03H9/02062 ,  H03H9/56

摘要： A method and apparatus for a piezoelectric resonator having combined thickness and width vibrational modes are disclosed. A piezoelectric resonator may include a piezoelectric substrate and a first electrode coupled to a first surface of the piezoelectric substrate. The piezoelectric resonator may further include a second electrode coupled to a second surface of the piezoelectric substrate, where the first surface and the second surface are substantially parallel and define a thickness dimension of the piezoelectric substrate. Furthermore, the thickness dimension and the width dimension of the piezoelectric substrate are configured to produce a resonance from a coherent combination of a thickness vibrational mode and a width vibrational mode when an excitation signal is applied to the electrodes.

摘要翻译： 公开了一种具有组合的厚度和宽度振动模式的压电谐振器的方法和装置。 压电谐振器可以包括压电衬底和耦合到压电衬底的第一表面的第一电极。 压电谐振器还可以包括耦合到压电基板的第二表面的第二电极，其中第一表面和第二表面基本平行并且限定压电基板的厚度尺寸。 此外，压电基板的厚度尺寸和宽度尺寸被构造成当激励信号施加到电极时，从厚度振动模式和宽度振动模式的相干组合产生谐振。

公开(公告)号：US20130021304A1

公开(公告)日：2013-01-24

申请号：US13186277

申请日：2011-07-19

申请人： Chengjie Zuo ,  Chi Shun Lo ,  Changhan Yun ,  Jonghae Kim

发明人： Chengjie Zuo ,  Chi Shun Lo ,  Changhan Yun ,  Jonghae Kim

IPC分类号： G06F3/038 ,  H01L41/047

CPC分类号： H03H9/173 ,  H03H9/02228

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. A resonator structure generally includes a first conductive layer with an input electrode, an output electrode, and a ground electrode. The ground electrode is disposed between the input electrode and the output electrode. In some implementations, the second conductive layer includes an input electrode, an output electrode, and a ground electrode. In some other implementations, a second conductive layer includes a pair of ground electrodes and a signal electrode in the form of an input or output electrode disposed between the ground electrodes. A piezoelectric layer is disposed between the first conductive layer and the second conductive layer. Sub-resonators can be defined in different regions of the structure, such that the piezoelectric layer is capable of moving to produce an output signal having frequencies at a first resonant frequency and a second resonant frequency.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 谐振器结构通常包括具有输入电极，输出电极和接地电极的第一导电层。 接地电极设置在输入电极和输出电极之间。 在一些实施方案中，第二导电层包括输入电极，输出电极和接地电极。 在一些其他实施方案中，第二导电层包括一对接地电极和设置在接地电极之间的输入或输出电极形式的信号电极。 压电层设置在第一导电层和第二导电层之间。 次谐振器可以在结构的不同区域中定义，使得压电层能够移动以产生具有第一谐振频率和第二谐振频率的频率的输出信号。

公开(公告)号：US07608534B2

公开(公告)日：2009-10-27

申请号：US11043580

申请日：2005-01-26

申请人： Changhan Yun ,  Javier Villarreal ,  Maurice S. Karpman

发明人： Changhan Yun ,  Javier Villarreal ,  Maurice S. Karpman

IPC分类号： H10L21/20 ,  H10L21/4763

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  B81C2203/0118 ,  H01L21/50 ,  H01L23/053 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： Bridge structures provide a surface on which to form interconnections to components through through-hole vias. The bridge structures at least partially, and preferably fully, span the gap between two wafers, and, more specifically, between a through-hole via in one wafer and a corresponding component on the other wafer. Bridge structure may be formed on the wafer having the through-hole via and/or the wafer having the component.

摘要翻译： 桥结构提供了一个表面，通过通孔通孔形成与组件的互连。 桥结构至少部分地，优选地完全跨越两个晶片之间的间隙，更具体地，在一个晶片中的通孔通孔和另一个晶片上的相应部件之间。 可以在具有通孔通孔和/或具有该部件的晶片的晶片上形成桥结构。

公开(公告)号：US20090029152A1

公开(公告)日：2009-01-29

申请号：US11828075

申请日：2007-07-25

申请人： Changhan Yun ,  Dewali Ray

发明人： Changhan Yun ,  Dewali Ray

IPC分类号： B32B5/16 ,  B32B37/14

CPC分类号： B81C1/00269 ,  B81C2203/0118 ,  Y10T156/10 ,  Y10T428/256

摘要： A method of forming a MEMS device includes providing a first wafer having a MEMS structure in a first area and a second wafer having a second area, applying a metal nanoparticle material between the first wafer and the second wafer, and bonding a portion of the first wafer to a portion of the second wafer with the metal nanoparticle material so as to form a sealed area in the first area and the second area.

摘要翻译： 形成MEMS器件的方法包括在第一区域中提供具有MEMS结构的第一晶片和具有第二区域的第二晶片，在第一晶片和第二晶片之间施加金属纳米颗粒材料，以及将第一 将晶片与金属纳米颗粒材料连接到第二晶片的一部分，以在第一区域和第二区域中形成密封区域。