公开(公告)号：US07534629B2

公开(公告)日：2009-05-19

申请号：US11448071

申请日：2006-06-07

申请人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Susumu Kasukabe

发明人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Susumu Kasukabe

IPC分类号： H01L21/66

CPC分类号： G01R1/0735

摘要： By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

摘要翻译： 通过使用通过使用半导体集成电路器件的制造技术形成的膜探针，将提高在多个芯片上共同执行的探测的产量。 通过使用多个推动器形成探针卡，每个推动器由POGO针绝缘体，POGO针，FPC连接器，膜探针HMS，冲击缓冲片，冲击缓冲板，芯片冷凝器YRS等形成 其中一个或两个POGO销按压布置成岛状的多个金属膜。 将一个或多个切口制成与膜探针区域中基本上平行于电连接到形成在膜探针中的探针的布线的延伸方向的方向匹配的待测芯片。

公开(公告)号：US07423439B2

公开(公告)日：2008-09-09

申请号：US11543021

申请日：2006-10-05

申请人： Susumu Kasukabe ,  Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Yasunori Narizuka

发明人： Susumu Kasukabe ,  Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Yasunori Narizuka

IPC分类号： G01R31/02

CPC分类号： G01R1/0735 ,  G01R3/00

摘要： In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.

摘要翻译： 一种证明卡，包括：探针片，其具有与设置在晶片上的电极接触的接触端子，从接触端子引出的布线和电连接到布线的电极; 以及多层布线基板，其具有与所述探针片的电极电连接的电极，其中，所述接触端子和所述晶片的电极之间的接触由一个或多个粘合保持器建立，所述粘合保持器从所述端子组的端子组的背面 端子触点，端子组通过具有弹簧的压块与电极焊盘接触。 通过组合粘合保持器，将探针片附接到粘合保持器和多个芯片的装置同时测试。

公开(公告)号：US20070103178A1

公开(公告)日：2007-05-10

申请号：US11543021

申请日：2006-10-05

申请人： Susumu Kasukabe ,  Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Yasunori Narizuka

发明人： Susumu Kasukabe ,  Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Yasunori Narizuka

IPC分类号： G01R31/02

CPC分类号： G01R1/0735 ,  G01R3/00

摘要： In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.

摘要翻译： 一种证明卡，包括：探针片，其具有与设置在晶片上的电极接触的接触端子，从接触端子引出的布线和电连接到布线的电极; 以及多层布线基板，其具有与所述探针片的电极电连接的电极，其中，所述接触端子和所述晶片的电极之间的接触由一个或多个粘合保持器建立，所述粘合保持器从所述端子组的端子组的背面 端子触点，端子组通过具有弹簧的压块与电极焊盘接触。 通过组合粘合保持器，将探针片附接到粘合保持器和多个芯片的装置同时测试。

公开(公告)号：US07219422B2

公开(公告)日：2007-05-22

申请号：US10765917

申请日：2004-01-29

申请人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

发明人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

IPC分类号： H05K3/00 ,  H01R9/00

CPC分类号： G01R1/07314 ,  G01R31/2872 ,  Y10T29/41 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49798

摘要： The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

摘要翻译： 半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成 待测 在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。 通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

公开(公告)号：US07351597B2

公开(公告)日：2008-04-01

申请号：US11750371

申请日：2007-05-18

申请人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

发明人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

IPC分类号： H01L21/66

CPC分类号： G01R1/07314 ,  G01R31/2872 ,  Y10T29/41 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49798

摘要： The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

摘要翻译： 半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成 待测 在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。 通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

公开(公告)号：US20070218572A1

公开(公告)日：2007-09-20

申请号：US11750371

申请日：2007-05-18

申请人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

发明人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

IPC分类号： H01L21/66

CPC分类号： G01R1/07314 ,  G01R31/2872 ,  Y10T29/41 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49798

摘要： The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

摘要翻译： 半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成 待测 在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。 通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

公开(公告)号：US20060281222A1

公开(公告)日：2006-12-14

申请号：US11448071

申请日：2006-06-07

申请人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka

发明人： Teruo Shoji ,  Akio Hasebe ,  Yoshinori Deguchi ,  Motoji Murakami ,  Masayoshi Okamoto ,  Yasunori Narizuka

IPC分类号： H01L21/00

CPC分类号： G01R1/0735

摘要： By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

公开(公告)号：US07235413B2

公开(公告)日：2007-06-26

申请号：US10968431

申请日：2004-10-20

申请人： Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

发明人： Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R3/00 ,  G01R1/07307 ,  G01R31/2889 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512

摘要： Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

摘要翻译： 降低在半导体集成电路器件的电气检查时对测试焊盘，层间绝缘膜，半导体元件或布线造成的任何损坏。 在薄膜探针的上表面上形成具有相对于待检查晶片的线膨胀率（热膨胀系数）大致相等的加强筋，在探针上方的加强件中切割槽，比第一弹性体柔软 第二弹性体被布置成填充凹槽并使槽溢出预定量，作为多层布线板的玻璃环氧树脂基板安装在第二弹性体上，并且设置在第二弹性体的上表面上的焊盘 作为属于薄膜探针的布线的一部分的玻璃环氧树脂基板和接合焊盘通过电线电连接。

公开(公告)号：US20070207559A1

公开(公告)日：2007-09-06

申请号：US11744309

申请日：2007-05-04

申请人： Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

发明人： Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

IPC分类号： H01L21/66

CPC分类号： G01R3/00 ,  G01R1/07307 ,  G01R1/0735 ,  G01R31/2889 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512

摘要： Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

摘要翻译： 降低在半导体集成电路器件的电气检查时对测试焊盘，层间绝缘膜，半导体元件或布线造成的任何损坏。 在薄膜探针的上表面上形成具有相对于待检查晶片的线膨胀率（热膨胀系数）大致相等的加强筋，在探针上方的加强件中切割槽，比第一弹性体柔软 第二弹性体被布置成填充凹槽并使槽溢出预定量，作为多层布线板的玻璃环氧树脂基板安装在第二弹性体上，并且设置在第二弹性体的上表面上的焊盘 作为属于薄膜探针的布线的一部分的玻璃环氧树脂基板和接合焊盘通过电线电连接。

公开(公告)号：US20050095734A1

公开(公告)日：2005-05-05

申请号：US10968431

申请日：2004-10-20

申请人： Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

发明人： Akio Hasebe ,  Yasunori Narizuka ,  Yasuhiro Motoyama ,  Teruo Shoji

IPC分类号： G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/66

CPC分类号： G01R3/00 ,  G01R1/07307 ,  G01R31/2889 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512

摘要： Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

摘要翻译： 降低在半导体集成电路器件的电气检查时对测试焊盘，层间绝缘膜，半导体元件或布线造成的任何损坏。 在薄膜探针的上表面上形成具有相对于待检查晶片的线膨胀率（热膨胀系数）大致相等的加强筋，在探针上方的加强件中切割槽，比第一弹性体柔软 第二弹性体被布置成填充凹槽并使槽溢出预定量，作为多层布线板的玻璃环氧树脂基板安装在第二弹性体上，并且设置在第二弹性体的上表面上的焊盘 作为属于薄膜探针的布线的一部分的玻璃环氧树脂基板和接合焊盘通过电线电连接。