公开(公告)号：US11121256B2

公开(公告)日：2021-09-14

申请号：US16894228

申请日：2020-06-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chih-Liang Chen ,  Lei-Chun Chou ,  Jack Liu ,  Kam-Tou Sio ,  Hui-Ting Yang ,  Wei-Cheng Lin ,  Chun-Hung Liou ,  Jiann-Tyng Tzeng ,  Chew-Yuen Young

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/088 ,  H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/417

摘要： A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.

公开(公告)号：US12034076B2

公开(公告)日：2024-07-09

申请号：US17406884

申请日：2021-08-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chih-Liang Chen ,  Lei-Chun Chou ,  Jack Liu ,  Kam-Tou Sio ,  Hui-Ting Yang ,  Wei-Cheng Lin ,  Chun-Hung Liou ,  Jiann-Tyng Tzeng ,  Chew-Yuen Young

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/76871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/41791

摘要： A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.

公开(公告)号：US11048848B2

公开(公告)日：2021-06-29

申请号：US16506501

申请日：2019-07-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Wei Peng ,  Chun-Hung Liou ,  Jiann-Tyng Tzeng

IPC分类号： G06F30/392 ,  G03F1/70 ,  G03F1/36 ,  G06F30/398 ,  G06F30/394

摘要： A method (of generating a layout diagram) includes: for a first cell which includes first and second active area patterns, a cell-boundary (CB) having first and second edge portions (EPs) substantially parallel to a vertical direction (VEPs), and first and second VEP-adjacent regions correspondingly adjacent the first and second VEPs: configuring the first VEP-adjacent region (VAR) to be a first active area (AA) continuous (AA-continuous) region in which the first active area pattern extends in a horizontal direction from an interior of the first cell to the first VEP; and configuring the second VAR to be a first AA-discontinuous region, the second active area pattern extending in the horizontal direction from the interior of the first cell towards the second VEP, and there being a first gap between a first end of the second active area pattern and the second VEP representing the first AA-discontinuous region.

公开(公告)号：US09917050B2

公开(公告)日：2018-03-13

申请号：US15331363

申请日：2016-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Meng-Hung Shen ,  Chun-Hung Liou ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

IPC分类号： G01R31/26 ,  H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L23/48 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/48 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66583 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

公开(公告)号：US20170040259A1

公开(公告)日：2017-02-09

申请号：US15331363

申请日：2016-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Meng-Hung Shen ,  Chun-Hung Liou ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

IPC分类号： H01L23/522 ,  H01L29/423 ,  H01L29/45 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/48 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66583 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

摘要翻译： 半导体器件包括具有源区和漏区的衬底以及布置在源区和漏区之间的沟道区。 该器件还包括在衬底上并与沟道区相邻的栅极结构。 栅极结构包括栅极堆叠，栅极堆叠的侧壁上的间隔物和栅极堆叠上的导体。 该器件还包括在衬底上的第一接触特征，并且电连接到源区和漏区中的至少一个。 第一接触特征的顶表面低于栅极结构的顶表面。 该装置还包括在第一接触特征上的第一介电层。 第一电介质层的顶表面与栅极结构的顶表面低于或基本上共平面。 导体在与第一介电层的平面图中最多部分重叠。

公开(公告)号：US10700207B2

公开(公告)日：2020-06-30

申请号：US15993149

申请日：2018-05-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chih-Liang Chen ,  Lei-Chun Chou ,  Jack Liu ,  Kam-Tou Sio ,  Hui-Ting Yang ,  Wei-Cheng Lin ,  Chun-Hung Liou ,  Jiann-Tyng Tzeng ,  Chew-Yuen Young

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L27/088 ,  H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/417

摘要： A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.

公开(公告)号：US09478636B2

公开(公告)日：2016-10-25

申请号：US14280196

申请日：2014-05-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Meng-Hung Shen ,  Chun-Hung Liou ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

IPC分类号： G01R31/26 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L23/48 ,  H01L21/8234

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/48 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66583 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

摘要翻译： 提供一种半导体器件及其形成方法。 半导体器件包括具有源极/漏极区域和源极/漏极区域之间的沟道区域的衬底; 在衬底上并且与沟道区相邻的栅极结构; 源极/漏极接触，并且电连接到源极/漏极区域; 以及源/漏触点上的接触保护层。 栅极结构包括栅极堆叠和间隔物。 源极/漏极触点的顶表面低于间隔物的顶表面，该顶表面与接触保护层的顶表面基本上共面。 当栅极通孔形成在栅极堆叠上时，接触保护层防止栅极堆叠与源极/漏极区域之间的意外短路。 因此，即使在从顶视图与沟道区域重叠的区域中，也可以在栅极堆叠的任何部分上形成栅极通孔。

公开(公告)号：US20150332962A1

公开(公告)日：2015-11-19

申请号：US14280196

申请日：2014-05-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Meng-Hung Shen ,  Chun-Hung Liou ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/48 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66583 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

摘要翻译： 提供一种半导体器件及其形成方法。 半导体器件包括具有源极/漏极区域和源极/漏极区域之间的沟道区域的衬底; 在衬底上并且与沟道区相邻的栅极结构; 源极/漏极接触，并且电连接到源极/漏极区域; 以及源/漏触点上的接触保护层。 栅极结构包括栅极堆叠和间隔物。 源极/漏极触点的顶表面低于间隔物的顶表面，该顶表面与接触保护层的顶表面基本上共面。 当栅极通孔形成在栅极堆叠上时，接触保护层防止栅极堆叠与源极/漏极区域之间的意外短路。 因此，即使在从顶视图与沟道区域重叠的区域中，也可以在栅极堆叠的任何部分上形成栅极通孔。