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公开(公告)号:US20150318225A1
公开(公告)日:2015-11-05
申请号:US14798857
申请日:2015-07-14
发明人: Ying-Ju CHEN , Hsien-Wei CHEN , Hao-Yi TSAI , Mirng-Ji LII
IPC分类号: H01L21/66 , H01L23/522 , H01L23/00 , H01L23/532 , H01L29/06 , H01L23/538 , H01L23/50 , H01L23/528
CPC分类号: H01L22/34 , H01L22/32 , H01L23/50 , H01L23/5226 , H01L23/5283 , H01L23/53209 , H01L23/53214 , H01L23/53228 , H01L23/5383 , H01L24/05 , H01L29/0649 , H01L2224/02166 , H01L2224/05093 , H01L2924/01013 , H01L2924/01029 , H01L2924/01074 , H01L2924/14 , H01L2924/00
摘要: A wafer including a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits. The wafer further includes a plurality of dielectric layers formed in the at least one scribe line having a process control monitor (PCM) pad structure formed therein, the PCM pad structure having: a plurality of metal pads interconnected by a plurality of conductive vias. The PCM pad further includes a plurality of contact bars in contact with a bottom-most metal pad, the contact bars extending substantially vertically from the bottom-most metal pad into the substrate. Additionally, the PCM pad includes an isolation structure substantially surrounding the plurality of contact bars to isolate the PCM pad structure.
摘要翻译: 包括具有形成在基板上方的多个集成电路的基板和在两个集成电路之间的至少一个划线的晶片。 所述晶片还包括形成在所述至少一个划线中的多个电介质层,其具有形成在其中的过程控制监视器(PCM)焊盘结构,所述PCM焊盘结构具有:通过多个导电通孔互连的多个金属焊盘。 PCM垫还包括与最底部金属垫接触的多个接触棒,接触杆从最底部的金属垫基本垂直地延伸到衬底中。 此外,PCM垫包括基本上围绕多个接触棒的隔离结构,以隔离PCM垫结构。
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公开(公告)号:US20190074255A1
公开(公告)日:2019-03-07
申请号:US16181130
申请日:2018-11-05
发明人: Hsien-Wei CHEN , Hao-Yi TSAI , Mirng-Ji LII , Chen-Hua YU
IPC分类号: H01L23/00 , H01L23/31 , H01L23/522 , H01L23/525
CPC分类号: H01L23/562 , H01L23/3114 , H01L23/3192 , H01L23/522 , H01L23/525 , H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02255 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05552 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/01079 , H01L2924/12042 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01013 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01047 , H01L2924/00
摘要: A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.
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公开(公告)号:US20170338188A1
公开(公告)日:2017-11-23
申请号:US15477717
申请日:2017-04-03
发明人: Hsien-Wei CHEN , Hao-Yi TSAI , Mirng-Ji LII , Chen-Hua YU
IPC分类号: H01L23/00 , H01L23/522 , H01L23/31 , H01L23/525
CPC分类号: H01L23/562 , H01L23/3114 , H01L23/3192 , H01L23/522 , H01L23/525 , H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02255 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05552 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/12042 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01013 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/01047 , H01L2924/00
摘要: A method of fabricating a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.
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公开(公告)号:US20220166254A1
公开(公告)日:2022-05-26
申请号:US17668648
申请日:2022-02-10
发明人: Chen-Hua YU , Hao-Yi TSAI , Tzu-Sung HUANG , Ming-Hung TSENG , Hung-Yi KUO
IPC分类号: H02J50/10 , H01F27/36 , H01L21/3205 , H01L23/10 , H01L23/31 , H01L23/498 , H01L23/522 , H01L23/538 , H01L23/64 , H02J7/00 , H04B5/00 , H01F38/14
摘要: A semiconductor device package is provided. The semiconductor device package includes a semiconductor device, a molding material surrounding the semiconductor device, and a conductive slot positioned over the molding material. The conductive slot has an opening and at least two channels connecting the opening to the edges of the conductive slot, and at least two of the channels extend in different directions.
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