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    STRESS RELIEF STRUCTURES IN PACKAGE ASSEMBLIES
    2.
    发明申请
    STRESS RELIEF STRUCTURES IN PACKAGE ASSEMBLIES 有权
    包装组合中的应力消除结构

    公开(公告)号：US20160190073A1

    公开(公告)日：2016-06-30

    申请号：US15062570

    申请日：2016-03-07

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hsien-Wei CHEN

    IPC分类号： H01L23/00 ,  H01L23/16 ,  H01L25/065

    CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3511 ,  H01L2924/00012

    摘要： A semiconductor package structure includes a substrate; and a die region having a plurality of dies disposed on the substrate. A first die of the plurality of dies is larger than a second die of the plurality of dies. The semiconductor package structure further includes a plurality of stress relief structures on the substrate. At least one stress relief structure of the plurality of stress relief structures is at a corner of the substrate. Each stress relief structure is spaced from a closest die of the plurality of dies by a first distance. Upper surfaces of each stress relief structure of the plurality of stress relief structures are unconnected.

    摘要翻译： 半导体封装结构包括：衬底; 以及具有设置在基板上的多个管芯的管芯区域。 多个模具的第一模具大于多个模具的第二模具。 半导体封装结构还包括在衬底上的多个应力释放结构。 多个应力释放结构中的至少一个应力释放结构位于基底的拐角处。 每个应力释放结构与多个模具中的最近的模具间隔开第一距离。 多个应力消除结构的每个应力消除结构的上表面是未连接的。

    METHODS OF MAKING INTEGRATED CIRCUITS
    3.
    发明申请
    METHODS OF MAKING INTEGRATED CIRCUITS 有权
    制造集成电路的方法

    公开(公告)号：US20140315383A1

    公开(公告)日：2014-10-23

    申请号：US14322122

    申请日：2014-07-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chung-Ying YANG ,  Hsien-Wei CHEN

    IPC分类号： H01L21/768 ,  H01L21/66

    CPC分类号： H01L21/76895 ,  H01L22/32 ,  H01L22/34 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making an integrated circuit including forming a seal ring structure around a circuit where the seal ring structure has a first portion and a tilted portion. The first portion of the seal ring structure is substantially parallel with an edge of the circuit. The tilted portion of the seal ring structure forms an obtuse angle with the first portion. The method further includes forming a first pad which is electrically coupled with the seal ring structure. The method further includes disposing a leakage current test structure in an area enclosed by the seal ring where at least one portion of the leakage current test structure is substantially parallel with the tilted portion of the seal ring structure. The method further includes forming a second pad which is electrically coupled with the leakage current test structure.

    摘要翻译： 一种制造集成电路的方法，包括在密封环结构具有第一部分和倾斜部分的电路周围形成密封环结构。 密封环结构的第一部分基本上与电路的边缘平行。 密封环结构的倾斜部分与第一部分形成钝角。 该方法还包括形成与密封环结构电耦合的第一焊盘。 该方法还包括在由密封环包围的区域中设置泄漏电流测试结构，其中泄漏电流测试结构的至少一部分基本上与密封环结构的倾斜部分平行。 该方法还包括形成与泄漏电流测试结构电耦合的第二焊盘。

    SEMICONDUCTOR STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20190295964A1

    公开(公告)日：2019-09-26

    申请号：US16442132

    申请日：2019-06-14

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Ming-Fa CHEN

    IPC分类号： H01L23/58 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

    摘要： A semiconductor structure includes a die, a molding surrounding the die, a first seal ring disposed over the molding, and a second seal ring disposed below the molding. The semiconductor structure further includes a first interconnect structure disposed below the first surface of the die and a second interconnect structure disposed over the second surface and the molding. The first seal ring is disposed in the second interconnect structure and disposed over the molding, and the second seal ring is provided within the die and the first interconnect structure.