摘要:
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.
摘要:
A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn-Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.
摘要:
A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.
摘要:
A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.
摘要:
A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface.
摘要:
A semiconductor device package is provided. The semiconductor device package includes a semiconductor device, a molding material surrounding the semiconductor device, and a conductive slot positioned over the molding material. The conductive slot has an opening and at least two channels connecting the opening to the edges of the conductive slot, and at least two of the channels extend in different directions.
摘要:
A semiconductor device includes an active device. The semiconductor device further includes a plurality of antenna grounds electrically connected to the active device. The semiconductor device further includes a plurality of patch antennas, wherein each patch antenna of the plurality of patch antennas is over a corresponding antenna ground of the plurality of antenna grounds. The semiconductor device further includes a plurality of reflectors, wherein each antenna ground of the plurality of antenna ground is between a corresponding patch antenna of the plurality of patch antennas and a corresponding reflector of the plurality of reflectors. An area of each antenna ground of the plurality of antenna grounds is greater than an area of each reflector of the plurality of reflectors.
摘要:
A package system comprising a first interconnect structure arranged over a first surface of a first substrate; a plurality of first through silicon via (TSV) structures in and extending through the first substrate; a molding compound material surrounding the first substrate; at least one through via in the molding compound material with the through via being offset from the first substrate in a direction parallel to the first surface; a second interconnect structure over a second surface of the first substrate; and a first integrated circuit mounted over the first surface of the substrate, with the first integrated circuit being electrically coupled to at least one of the first TSV structures through the first interconnect structure and a connecting bump while the first interconnection structure is electrically coupled to the through via. The first interconnect structure may also be configured for mounting one or more integrated circuits and/or a second interposer on a surface opposite that of the first interposer.
摘要:
A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
摘要:
A semiconductor device includes a device die, a first power supply die, and a second power supply die different from the first power supply die. The device die includes a first circuit and a second circuit. The first power supply die is electrically coupled to the first circuit and configured to supply power for the first circuit. The second power supply die is electrically coupled to the second circuit and configured to supply power for the second circuit. The first and second power supply dies are attached to the device die, and overlap the device die in a thickness direction of the device die.