公开(公告)号：US20190006183A1

公开(公告)日：2019-01-03

申请号：US16042527

申请日：2018-07-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： SHIU-KO JANGJIAN ,  TING-CHUN WANG ,  CHI-CHERNG JENG ,  CHI-WEN LIU

IPC分类号： H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/02183 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary method includes forming a gate stack over a substrate and at least partially removing the gate stack, thereby forming an opening. A multi-function layer is deposited in the opening and a work function layer is deposited over the multi-function layer. The multi-function layer includes nitrogen and one of titanium or tantalum. The work function layer includes nitrogen and one of titanium or tantalum. A concentration of the nitrogen of the work function layer is different than a concentration of the nitrogen of the multi-function layer. In some implementations, the concentration of the nitrogen of the work function layer from about 2% to about 5% and the concentration of the nitrogen of the multi-function layer from about 5% to about 15%.

公开(公告)号：US20150054029A1

公开(公告)日：2015-02-26

申请号：US14532228

申请日：2014-11-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： SHIU-KO JANGJIAN ,  TING-CHUN WANG ,  CHI-CHERNG JENG ,  CHI-WEN LlU

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L27/088 ,  H01L29/10

CPC分类号： H01L21/28088 ,  H01L21/02183 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.

摘要翻译： 集成电路器件包括半导体衬底; 以及设置在半导体衬底上的栅极堆叠。 栅极堆叠还包括设置在半导体衬底上的栅极电介质层; 设置在所述栅极介电层上的多功能阻挡/润湿层，其中所述多功能阻挡/润湿层包括钽铝氮化物（TaAlCN）; 设置在多功能阻挡/润湿层上的功函数层; 以及设置在功函数层上的导电层。

公开(公告)号：US20200090938A1

公开(公告)日：2020-03-19

申请号：US16685800

申请日：2019-11-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： SHIU-KO JANGJIAN ,  TING-CHUN WANG ,  CHI-CHERNG JENG ,  CHI-WEN LIU

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161

摘要： Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.

公开(公告)号：US20150228720A1

公开(公告)日：2015-08-13

申请号：US14178814

申请日：2014-02-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHEN-CHUN CHEN ,  CHIU-JUNG CHEN ,  FU-TSUN TSAI ,  SHIU-KO JANGJIAN ,  CHI-CHERNG JENG ,  HSIN-CHI CHEN

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L23/00

CPC分类号： H01L24/83 ,  H01L21/02019 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/76256 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/83201 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2924/07025

摘要： A semiconductor structure includes a wafer including a first surface and a periphery, a plurality of protrusions protruded from the first surface and a plurality of recesses spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the periphery of the wafer and is elongated across the first surface of the wafer.

摘要翻译： 半导体结构包括：第一表面和周边的晶片，从第一表面突出的多个突起和由多个突起彼此间隔开的多个凹部，并且多个凹部中的每一个从周边延伸 并且延伸穿过晶片的第一表面。

公开(公告)号：US20180144943A1

公开(公告)日：2018-05-24

申请号：US15875244

申请日：2018-01-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： RU-SHANG HSIAO ,  CHI-CHERNG JENG ,  CHIH-MU HUANG

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L21/28114 ,  H01L21/28247 ,  H01L29/42376 ,  H01L29/66545

摘要： A semiconductor structure includes a first layer having a recessed surface, a metal layer disposed above the first layer, and a second layer disposed above the metal layer and confined by the recessed surface. The second layer includes a first lateral side and a second lateral side. A first thickness of the second layer in a middle portion between the first lateral side and the second lateral side is less than a second thickness of at least one of the first lateral side and the second lateral side of the second layer. The metal layer has a same material across an entire range covered by the second layer.

公开(公告)号：US20160315065A1

公开(公告)日：2016-10-27

申请号：US15203045

申请日：2016-07-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHEN-CHUN CHEN ,  CHIU-JUNG CHEN ,  FU-TSUN TSAI ,  SHIU-KO JANGJIAN ,  CHI-CHERNG JENG ,  HSIN-CHI CHEN

IPC分类号： H01L23/00 ,  H01L27/146 ,  H01L21/027 ,  H01L21/306 ,  H01L21/268

CPC分类号： H01L24/83 ,  H01L21/02019 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/76256 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/83201 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2924/07025

摘要： A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.

摘要翻译： 制造半导体结构的方法包括提供包括表面的第一晶片，去除表面上的第一晶片的一些部分以形成在第一晶片的表面的至少一部分上延伸的多个凹槽，从而提供第二晶片 并且将第二晶片设置在第一晶片的表面上。

公开(公告)号：US20160276158A1

公开(公告)日：2016-09-22

申请号：US14658667

申请日：2015-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： RU-SHANG HSIAO ,  CHI-CHERNG JENG ,  CHIH-MU HUANG

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28114 ,  H01L21/28247 ,  H01L29/42376 ,  H01L29/66545

摘要： A semiconductor structure comprising a first layer, a metal layer and a second layer is disclosed. The first layer comprises a recessed surface. The metal layer is above a portion of the recessed surface. The second layer is above the metal layer and confined by the recessed surface. The second layer comprises a top surface, a first lateral side and a second lateral side. The etch rate of an etchant with respect to the metal layer is greater than the etch rate of the etchant with respect to the second layer. The thickness of the second layer in the middle of the second layer is less than the thickness of the second layer at the first lateral side or the second lateral side. A method of forming a semiconductor structure is disclosed.

摘要翻译： 公开了一种包括第一层，金属层和第二层的半导体结构。 第一层包括凹陷表面。 金属层位于凹入表面的一部分之上。 第二层位于金属层的上方并被凹入的表面限制。 第二层包括顶表面，第一侧面和第二横向侧面。 蚀刻剂相对于金属层的蚀刻速率大于蚀刻剂相对于第二层的蚀刻速率。 第二层中间的第二层的厚度小于第一侧面或第二侧面处的第二层的厚度。 公开了一种形成半导体结构的方法。

公开(公告)号：US20190287806A1

公开(公告)日：2019-09-19

申请号：US16429595

申请日：2019-06-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： RU-SHANG HSIAO ,  CHI-CHERNG JENG ,  CHIH-MU HUANG

IPC分类号： H01L21/28 ,  H01L29/423

摘要： A semiconductor structure and a method of forming the same are provided. According to an aspect of the disclosure, a semiconductor structure includes a first layer having a bottom portion and a sidewall connected to the bottom portion, a metal layer disposed above the bottom portion of the first layer, and a second layer disposed above the metal layer and laterally surrounded by the sidewall of the first layer. The metal layer includes a periphery and a middle portion surrounded by the periphery, the middle portion being thicker than the periphery, and a first etch rate of an etchant with respect to the metal layer is uniform throughout the metal layer and is greater than a second etch rate of the etchant with respect to the second layer.

公开(公告)号：US20180277672A1

公开(公告)日：2018-09-27

申请号：US15986619

申请日：2018-05-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： RU-SHANG HSIAO ,  CHI-CHERNG JENG ,  CHIH-MU HUANG

IPC分类号： H01L29/78 ,  H01L23/31 ,  H01L23/29 ,  H01L29/735

摘要： A semiconductor structure includes a substrate, a source/drain region, a composite layer and a plug. The source/drain region and the composite layer are over the substrate. The composite layer includes a first sublayer having a first material, a second sublayer having a second material, and a third sublayer having the first material. A bandgap of the second material is larger than that of the first material. The second sublayer is between the first sublayer and the third sublayer. The plug is through the composite layer, and electrically connected to the source/drain region. The plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer, and a first width of the first portion and a third width of the third portion is smaller than a second width of the second portion.

公开(公告)号：US20160254157A1

公开(公告)日：2016-09-01

申请号：US15149978

申请日：2016-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： SHIU-KO JANGJIAN ,  TING-CHUN WANG ,  CHI-CHERNG JENG ,  CHI-WEN LIU

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L21/28088 ,  H01L21/02183 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A method includes forming a gate stack over a semiconductor substrate; forming an interlayer dielectric layer surrounding the gate stack; and at least partially removing the gate stack, thereby forming an opening. The method further includes forming a multi-function wetting/blocking layer in the opening, a work function layer over the multi-function blocking/wetting layer, and a conductive layer over the work function layer. The work function layer, the multi-function wetting/blocking layer, and the conductive layer fill the opening. The multi-function wetting/blocking layer includes aluminum, carbon, nitride, and one of: titanium and tantalum.

摘要翻译： 一种方法包括在半导体衬底上形成栅叠层; 形成围绕所述栅叠层的层间绝缘层; 并且至少部分地移除栅极堆叠，从而形成开口。 该方法还包括在开口中形成多功能润湿/阻挡层，在多功能阻挡/润湿层上形成功函数层，以及在功函数层上形成导电层。 工作功能层，多功能润湿/阻挡层和导电层填充开口。 多功能润湿/阻挡层包括铝，碳，氮化物，以及钛和钽之一。