公开(公告)号：US12027526B2

公开(公告)日：2024-07-02

申请号：US17949266

申请日：2022-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

公开(公告)号：US20230014120A1

公开(公告)日：2023-01-19

申请号：US17949266

申请日：2022-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/84 ,  H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L29/423

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

公开(公告)号：US20160260704A1

公开(公告)日：2016-09-08

申请号：US14638407

申请日：2015-03-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ker-Hsiao Huo ,  Hsin-Chih Chiang ,  Kevin Chen ,  Chun Lin Tsai ,  Yi-Min Chen

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/76202 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high voltage semiconductor device includes: a source having a first conductivity type and a drain having the first conductivity type disposed in a substrate; a first dielectric component disposed on a surface of the substrate between the source and the drain; a drift region disposed in the substrate, wherein the drift region has the first conductivity type; a first doped region having a second conductivity type and disposed within the drift region under the dielectric component, the second conductivity type being opposite the first conductivity type; a second doped region having the second conductivity type and disposed within the drift region, wherein the second doped region at least partially surrounds one of the source and the drain; a resistor disposed directly on the dielectric component; and a gate disposed directly on the dielectric component, wherein the gate is electrically coupled to the resistor.

Abstract translation: 高电压半导体器件包括：具有第一导电类型的源极和具有设置在衬底中的第一导电类型的漏极; 设置在源极和漏极之间的衬底的表面上的第一介电部件; 设置在所述衬底中的漂移区，其中所述漂移区具有第一导电类型; 第一掺杂区域，具有第二导电类型并且设置在介电部件下方的漂移区域内，第二导电类型与第一导电类型相反; 具有第二导电类型并且设置在漂移区内的第二掺杂区，其中第二掺杂区至少部分地围绕源极和漏极之一; 直接设置在电介质部件上的电阻器; 以及直接设置在所述电介质部件上的栅极，其中所述栅极电耦合到所述电阻器。

公开(公告)号：US11414763B2

公开(公告)日：2022-08-16

申请号：US16706054

申请日：2019-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Ta Lei ,  Chia-Hua Chu ,  Hsin-Chih Chiang ,  Tung-Tsun Chen ,  Chun-Wen Cheng

IPC: G01N33/00 ,  G01N27/12 ,  C23F4/00

Abstract: The present disclosure provides a method of manufacturing a gas sensor. The method includes the following operations: a substrate is received; a conductor layer is formed over the substrate; the conductor layer is patterned to form a conductor with a plurality of openings by an etching operation, the openings being arranged in a repeating pattern, a minimal dimension of the opening being about 4 micrometers; and a gas-sensing film is formed over the conductor.

公开(公告)号：US10508345B2

公开(公告)日：2019-12-17

申请号：US14879018

申请日：2015-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Ta Lei ,  Chia-Hua Chu ,  Hsin-Chih Chiang ,  Tung-Tsun Chen ,  Chun-Wen Cheng

IPC: C23F4/00

Abstract: Some embodiments of the present disclosure provide a gas sensor in an IOT. The gas sensor includes a substrate, a conductor disposed above the substrate, and a sensing film disposed over the conductor. The conductor has a top-view pattern including a plurality of openings, a minimal dimension of the opening being less than about 4 micrometer; and a perimeter enclosing the opening. Some embodiments of the present disclosure provide a method of manufacturing a gas sensor. The method includes receiving a substrate; forming a conductor, over the substrate; patterning the conductor to form a plurality of openings in the conductor by an etching operation, and forming a gas-sensing film over the conductor. The openings are arranged in a repeating pattern, and a minimal dimension of the opening being about 4 micrometer.

公开(公告)号：US09379179B2

公开(公告)日：2016-06-28

申请号：US14079715

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/861 ,  H01L27/02

CPC classification number: H01L27/0255 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/66121 ,  H01L29/861

Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region. The device further comprises a second electrode electrically connected to the fourth semiconductor region and to the fifth semiconductor region.

Abstract translation: 配置成提供增加的电流增益的半导体器件包括具有第一导电类型的半导体衬底。 该器件还包括具有第二导电类型的第一半导体区域。 该器件还包括在第一半导体区域中具有第一导电类型的第二半导体区域。 该器件还包括具有第二导电类型的第一半导体区域中的第三半导体区域。 该器件还包括具有第一导电类型的第一半导体区域之外的第四半导体区域。 该器件还包括与第四半导体区域相邻并具有第二导电类型的第一半导体区域外的第五半导体区域。 该装置还包括电连接到第三半导体区域的第一电极。 该器件还包括电连接到第四半导体区域和第五半导体区域的第二电极。

公开(公告)号：US20240321894A1

公开(公告)日：2024-09-26

申请号：US18668333

申请日：2024-05-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first well region, a second well region, and a third well region disposed within a semiconductor substrate. The second well region is disposed between the first and second well regions. A first source/drain region is in the first well region. A second source/drain region is in the second well region. A gate structure is on the semiconductor substrate and spaced laterally between the first and second source/drain regions. A contact region is disposed in the third well region. A conductive structure is on the semiconductor substrate and spaced laterally between the second source/drain region and the contact region.

公开(公告)号：US10014288B2

公开(公告)日：2018-07-03

申请号：US15173835

申请日：2016-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/66121 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor substrate. A first semiconductor region is over a portion of the semiconductor substrate to a first depth. A second semiconductor region is in the first semiconductor region. A third semiconductor region is in the first semiconductor region. A fourth semiconductor region is outside the first semiconductor region. A fifth semiconductor region is outside the first semiconductor region to a fifth depth, the fifth semiconductor region being adjacent the fourth semiconductor region. A sixth semiconductor region is below the fifth semiconductor region and to a sixth depth. The sixth depth is equal to the first depth. A first electrode is connected to the third semiconductor region. A second electrode is connected to the fourth and fifth semiconductor regions. The fifth semiconductor region is configured to cause an increase in a current during a cathode to anode positive bias operation between the first and second electrodes.

公开(公告)号：US11987891B2

公开(公告)日：2024-05-21

申请号：US17844080

申请日：2022-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Ta Lei ,  Chia-Hua Chu ,  Hsin-Chih Chiang ,  Tung-Tsun Chen ,  Chun-Wen Cheng

IPC: G01N33/00 ,  C23F4/00 ,  G01N27/12

CPC classification number: C23F4/00 ,  G01N27/128 ,  G01N33/0075

Abstract: The present disclosure provides a gas sensor. The gas sensor includes a substrate, a conductor layer over the substrate, wherein the conductor layer includes a conductive pattern including a plurality of openings, the openings being arranged in a repeating pattern, an insulating layer in the plurality of openings and over a top surface of the conductive pattern, wherein the conductive pattern is embedded in the insulating layer, and a gas sensing film over a portion of the insulating layer.

公开(公告)号：US09431531B2

公开(公告)日：2016-08-30

申请号：US14089803

申请日：2013-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Yang Lin ,  Hsin-Chih Chiang ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L29/78 ,  H01L21/74 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L21/743 ,  H01L29/1087 ,  H01L29/78624

Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.

Abstract translation: 配置为提供高散热并改善击穿电压的半导体器件包括衬底，衬底上的掩埋氧化物层，掩埋氧化物层下面的衬底中的掩埋的n +区，以及在掩埋氧化物层上的外延层。 外延层包括p阱，n阱以及p阱和n阱之间的漂移区。 半导体器件还包括源极接触，将源极接触电连接到p阱的第一电极以及p阱的一部分和漂移区的一部分上的栅极。 半导体器件还包括漏极接触，以及从漏极接触通过n阱延伸并穿过掩埋氧化物层到掩埋的n +区域的第二电极。 第二电极将漏极接触电连接到n阱和掩埋的n +区域。