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公开(公告)号：US20240355784A1
公开(公告)日：2024-10-24
申请号：US18758167
申请日：2024-06-28
发明人： Kuo-Ming Wu , Ching-Chun Wang , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Yung-Lung Lin , Shih-Han Huang , I-Nan Chen
IPC分类号： H01L25/065 , H01L23/00 , H01L23/48 , H01L23/528 , H01L23/532 , H01L25/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/528 , H01L23/53209 , H01L24/33 , H01L24/83 , H01L25/50
摘要： A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.
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公开(公告)号：US20240313010A1
公开(公告)日：2024-09-19
申请号：US18679526
申请日：2024-05-31
发明人： Seiji Takahashi , Chen-Jong Wang , Dun-Nian Yaung , Feng-Chi Hung , Feng-Jia Shiu , Jen-Cheng Liu , Jhy-Jyi Sze , Chun-Wei Chang , Wei-Cheng Hsu , Wei Chuang Wu , Yimin Huang
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L27/1464 , H01L27/14641 , H01L27/14689
摘要： In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.
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公开(公告)号：US20240266219A1
公开(公告)日：2024-08-08
申请号：US18613592
申请日：2024-03-22
发明人： Min-Feng Kao , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481
摘要： Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.
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公开(公告)号：US12034037B2
公开(公告)日：2024-07-09
申请号：US17867819
申请日：2022-07-19
发明人： Min-Feng Kao , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu
IPC分类号： H01L23/48 , H01L21/8234 , H01L23/00 , H01L23/522 , H01L23/528 , H01L25/00 , H01L25/065 , H01L27/06 , H01L49/02
CPC分类号： H01L28/91 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/528 , H01L24/08 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L27/0629 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2225/06565
摘要： Some embodiments relate to a method. In the method, semiconductor devices are formed on a frontside of a semiconductor substrate. A trench is formed in a backside of the semiconductor substrate. Conductive and insulating layers are alternatingly formed in the trench on the backside of the semiconductor substrate to establish a backside capacitor. A backside interconnect structure is formed on the backside of the semiconductor substrate to couple to capacitor electrodes of the backside capacitor.
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公开(公告)号：US20240136401A1
公开(公告)日：2024-04-25
申请号：US18405099
申请日：2024-01-05
发明人： Yin-Kai Liao , Sin-Yi Jiang , Hsiang-Lin Chen , Yi-Shin Chu , Po-Chun Liu , Kuan-Chieh Huang , Jyh-Ming Hung , Jen-Cheng Liu
IPC分类号： H01L29/10 , H01L29/167 , H01L29/49 , H01L29/66
CPC分类号： H01L29/1087 , H01L29/167 , H01L29/4933 , H01L29/6659
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.
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公开(公告)号：US20240087988A1
公开(公告)日：2024-03-14
申请号：US18511016
申请日：2023-11-16
IPC分类号： H01L23/48 , H01L21/308 , H01L21/768 , H01L23/522
CPC分类号： H01L23/481 , H01L21/308 , H01L21/76804 , H01L21/76831 , H01L21/76898 , H01L23/5226
摘要： The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.
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公开(公告)号：US11901396B2
公开(公告)日：2024-02-13
申请号：US17154912
申请日：2021-01-21
发明人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Wen-De Wang , Hsiao-Hui Tseng
IPC分类号： H01L27/146 , H01L23/48 , H01L23/00 , H01L23/525
CPC分类号： H01L27/14687 , H01L27/1464 , H01L27/14632 , H01L27/14636 , H01L27/14638 , H01L27/14645 , H01L27/14683 , H01L27/14689 , H01L23/481 , H01L23/525 , H01L24/83 , H01L27/14623
摘要： Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
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公开(公告)号：US11901387B2
公开(公告)日：2024-02-13
申请号：US17369567
申请日：2021-07-07
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
IPC分类号： H01L27/146 , H01L21/762
CPC分类号： H01L27/1463 , H01L21/76224 , H01L27/14621 , H01L27/14627 , H01L27/14683
摘要： A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
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公开(公告)号：US20240021645A1
公开(公告)日：2024-01-18
申请号：US18356672
申请日：2023-07-21
发明人： Jeng-Shyan Lin , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang , Wei-Chih Weng , Yu-Yang Shen
IPC分类号： H01L27/146 , H01L23/48 , H01L21/768 , H01L23/00 , H01L21/78 , H01L23/528 , H01L25/065 , H01L25/00
CPC分类号： H01L27/14634 , H01L23/481 , H01L21/76898 , H01L24/00 , H01L21/78 , H01L23/5283 , H01L25/0657 , H01L25/50 , H01L27/1463 , H01L27/14636 , H01L27/1469 , H01L23/53223
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.
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公开(公告)号：US11817470B2
公开(公告)日：2023-11-14
申请号：US17349120
申请日：2021-06-16
发明人： Jeng-Shyan Lin , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang , Wei-Chih Weng , Yu-Yang Shen
IPC分类号： H01L27/146 , H01L23/48 , H01L23/00 , H01L23/528 , H01L25/065 , H01L25/00 , H01L23/532 , H01L21/768 , H01L21/78
CPC分类号： H01L27/14634 , H01L21/76898 , H01L21/78 , H01L23/481 , H01L23/5283 , H01L24/00 , H01L25/0657 , H01L25/50 , H01L27/1463 , H01L27/1469 , H01L27/14636 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2224/80895 , H01L2224/80896
摘要： The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.
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