公开(公告)号：US11682628B2

公开(公告)日：2023-06-20

申请号：US16711047

申请日：2019-12-11

Applicant: TDK Corporation

Inventor： Kazutoshi Tsuyutani ,  Masashi Katsumata ,  Yoshihiro Suzuki

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/16 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/09 ,  H01L25/16 ,  H01L2224/08225 ,  H01L2224/0903 ,  H01L2224/0913

Abstract: Disclosed herein is a semiconductor IC-embedded substrate that includes insulating layers, conductor layers, and a semiconductor IC embedded in the insulating layers. The insulating layers includes first and second insulating layers. The conductor layers includes a first conductor layer having a first wiring pattern and a second conductor layer having a second wiring pattern. The semiconductor IC includes a rewiring pattern connected in common to power supply pads. The rewiring pattern is connected to the first wiring pattern via a first opening of the first insulating layer. The first wiring pattern is connected to the second wiring pattern via second openings of the second insulating layer. The first opening is greater in area than each of the second openings.

公开(公告)号：US12125754B2

公开(公告)日：2024-10-22

申请号：US17894584

申请日：2022-08-24

Applicant: TDK CORPORATION

Inventor： Kazutoshi Tsuyutani ,  Yoshihiro Suzuki ,  Akira Motohashi

IPC: H01L23/13 ,  G01H3/00 ,  G01K13/02 ,  G01L9/00 ,  G01N33/00 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/13 ,  G01H3/00 ,  G01K13/02 ,  G01L9/0041 ,  G01N33/0027 ,  H01L23/5389 ,  H01L25/18

Abstract: A sensor package substrate disclosed in the present specification has a mounting area in which a sensor chip is mounted and a controller chip connected to the sensor chip. A through hole is formed in the sensor package substrate so as to overlap the mounting area in a plan view and to penetrate the substrate from one surface to the other surface thereof. The mounting area and the controller chip overlap each other in a plan view. According to the present invention, by reducing the thickness of an insulating layer, it is possible not only to reduce the distance of a wiring for the sensor chip and controller chip, but also to reduce the area of the substrate.

公开(公告)号：US10515898B2

公开(公告)日：2019-12-24

申请号：US15978443

申请日：2018-05-14

Applicant: TDK CORPORATION

Inventor： Kazutoshi Tsuyutani ,  Masashi Katsumata

IPC: H01L23/538 ,  H01L23/00

Abstract: Disclosed herein is a circuit board that includes a first insulating layer having an upper surface; a first wiring layer embedded in the first insulating layer, the first wiring layer having an upper surface exposed from the upper surface of the first insulating layer such that the upper surface of the first wiring layer is substantially coplanar with the upper surface of the first insulating layer; a semiconductor IC mounted on the upper surface of the first wiring layer with a die attach material interposed therebetween; and a second insulating layer stacked on the upper surface of the first wiring layer so as to embed the semiconductor IC, wherein a bottom surface of the die attach material is in contact with both of the upper surface of the first insulating layer and the upper surface of the first wiring layer.

公开(公告)号：US10917974B2

公开(公告)日：2021-02-09

申请号：US14054556

申请日：2013-10-15

Applicant: TDK Corporation

Inventor： Kazutoshi Tsuyutani

IPC: H05K5/00 ,  H05K1/18 ,  H05K3/42 ,  H05K3/30 ,  H05K1/11 ,  H01L23/00

Abstract: Disclosed herein is a circuit board that includes a resin substrate including a substrate wiring layer, and an electronic component embedded in the resin substrate and having a plurality of external electrodes. The resin substrate includes a plurality of via holes that expose the external electrodes and a plurality of via conductors embedded in the via holes to electrically connect the substrate wiring layer to the external electrodes. At least some of the via holes are different in planar shape from each other.

公开(公告)号：US09635756B2

公开(公告)日：2017-04-25

申请号：US14032093

申请日：2013-09-19

Applicant: TDK Corporation

Inventor： Kazutoshi Tsuyutani ,  Hiroshige Ohkawa ,  Yoshihiro Suzuki ,  Tsuyoshi Mochizuki

IPC: H05K1/16 ,  H05K1/03 ,  H05K3/30 ,  H05K1/18 ,  H05K3/00 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56 ,  H01L23/495

CPC classification number: H05K1/03 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49572 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/188 ,  H05K3/007 ,  H05K3/305 ,  H05K2201/068 ,  H05K2203/0152 ,  Y10T29/4913

Abstract: Disclosed herein is a manufacturing method of a circuit board. The manufacturing method includes a first step for preparing a prepreg in which a core material is impregnated with an uncured resin. The prepreg has a through-hole surrounded by the core material and the resin so as to penetrate through the core material and the resin. The manufacturing method further includes a second step for housing a semiconductor IC in the through-hole, and a third step for pressing the prepreg so that a part of the resin flows into the through-hole to allow the semiconductor IC housed in the through-hole to be embedded in the resin.

公开(公告)号：US09153553B2

公开(公告)日：2015-10-06

申请号：US14555325

申请日：2014-11-26

Applicant: TDK Corporation

Inventor： Kazutoshi Tsuyutani ,  Masashi Katsumata

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4918 ,  H01L2224/83132 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Disclosed herein is an IC embedded substrate that includes a core substrate having an opening, an IC chip provided in the opening, a lower insulating layer, and upper insulating layer. The IC chip and the core substrate is sandwiched between the lower insulating layer and the upper insulating layer. The upper insulating layer is formed in such a way as to fill a gap between a side surface of the IC chip and an inner peripheral surface of the opening of the core substrate. A first distance from the upper surface of the IC chip to an upper surface of the upper insulating layer is shorter than a second distance from the upper surface of the core substrate to the upper surface of the upper insulating layer.

Abstract translation: 这里公开了一种IC嵌入式基板，其包括具有开口的芯基板，设置在开口中的IC芯片，下绝缘层和上绝缘层。 IC芯片和芯基板夹在下绝缘层和上绝缘层之间。 上绝缘层以填充IC芯片的侧表面和芯基板的开口的内周表面之间的间隙的方式形成。 从IC芯片的上表面到上绝缘层的上表面的第一距离短于从芯基板的上表面到上绝缘层的上表面的第二距离。

公开(公告)号：US12240751B2

公开(公告)日：2025-03-04

申请号：US17620485

申请日：2020-06-05

Applicant: TDK Corporation

Inventor： Kazutoshi Tsuyutani ,  Yoshihiro Suzuki

IPC: H01L21/48 ,  B81B7/00 ,  B81C1/00 ,  G01D11/24 ,  H01L23/498 ,  H04R1/04 ,  H04R19/04

Abstract: A sensor package substrate has through holes V1 and V2 at a position overlapping a sensor chip mounting area. The through hole V1 has a minimum inner diameter at a depth position D1, and the through hole V2 has a minimum inner diameter at a depth position D2 different from the depth position D1. Thus, since the plurality of through holes are formed at a position overlapping the sensor chip mounting area, the diameter of each of the through holes can be reduced. This makes foreign matters unlikely to enter through the through holes, and a reduction in the strength of the substrate is suppressed. In addition, since the depth position D1 and depth position D2 are located at different depth levels, it is possible to sufficiently maintain the strength of a part of the substrate that is positioned between the through holes V1 and V2.

公开(公告)号：US11462447B2

公开(公告)日：2022-10-04

申请号：US16550995

申请日：2019-08-26

Applicant: TDK CORPORATION

Inventor： Kazutoshi Tsuyutani ,  Yoshihiro Suzuki ,  Akira Motohashi

IPC: H01L23/13 ,  H01L25/18 ,  H01L23/538 ,  G01L9/00 ,  G01H3/00 ,  G01K13/02 ,  G01N33/00 ,  G01K13/024

Abstract: A sensor package substrate disclosed in the present specification has a mounting area in which a sensor chip is mounted and a controller chip connected to the sensor chip. A through hole is formed in the sensor package substrate so as to overlap the mounting area in a plan view and to penetrate the substrate from one surface to the other surface thereof. The mounting area and the controller chip overlap each other in a plan view. According to the present invention, by reducing the thickness of an insulating layer, it is possible not only to reduce the distance of a wiring for the sensor chip and controller chip, but also to reduce the area of the substrate.

公开(公告)号：US11053118B2

公开(公告)日：2021-07-06

申请号：US16587794

申请日：2019-09-30

Applicant: TDK CORPORATION

Inventor： Kazutoshi Tsuyutani ,  Yoshihiro Suzuki

IPC: H01L23/00 ,  B81C1/00 ,  B81B7/02 ,  H04R19/04 ,  H04R19/00

Abstract: Disclosed herein is a sensor package substrate that includes a first mounting area for mounting a sensor chip. The sensor package substrate has a through hole formed at a position overlapping the first mounting area in a plan view so as to penetrate the sensor package substrate from one surface to the other surface. The through hole includes a first section having a first diameter and a second section having a second diameter smaller than the first diameter. A step part inside the through hole positioned at a boundary between the first and second sections constitutes a second mounting area for mounting an anti-dust filter.

公开(公告)号：US20180337131A1

公开(公告)日：2018-11-22

申请号：US15978443

申请日：2018-05-14

Applicant: TDK CORPORATION

Inventor： Kazutoshi Tsuyutani ,  Masashi Katsumata

IPC: H01L23/538 ,  H01L23/00

Abstract: Disclosed herein is a circuit board that includes a first insulating layer having an upper surface; a first wiring layer embedded in the first insulating layer, the first wiring layer having an upper surface exposed from the upper surface of the first insulating layer such that the upper surface of the first wiring layer is substantially coplanar with the upper surface of the first insulating layer; a semiconductor IC mounted on the upper surface of the first wiring layer with a die attach material interposed therebetween; and a second insulating layer stacked on the upper surface of the first wiring layer so as to embed the semiconductor IC, wherein a bottom surface of the die attach material is in contact with both of the upper surface of the first insulating layer and the upper surface of the first wiring layer.