公开(公告)号：US20220246566A1

公开(公告)日：2022-08-04

申请号：US17162189

申请日：2021-01-29

Applicant: Texas Instruments Incorporated

Inventor： Suvadip Banerjee ,  John Paul Tellkamp

IPC: H01L23/00 ,  H01L23/488 ,  H01L23/528 ,  H01L21/48

Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

公开(公告)号：US12009336B2

公开(公告)日：2024-06-11

申请号：US17390823

申请日：2021-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahmud Halim Chowdhury ,  Amin Sijelmassi ,  Murali Kittappa ,  Anindya Poddar ,  Honglin Guo ,  Joe Adam Garcia ,  John Paul Tellkamp

IPC: H01L23/00 ,  H01H85/02 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L24/48 ,  H01H85/0241 ,  H01L24/49 ,  H01L24/85 ,  H01H2085/0283 ,  H01L23/49555 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/4801 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/4846 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/49111 ,  H01L2224/494 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/8534 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/2064 ,  H01L2924/2075

Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

公开(公告)号：US11557722B2

公开(公告)日：2023-01-17

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  G01R33/07 ,  G01R15/20 ,  H01L43/06 ,  H01L23/495 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US20210287970A1

公开(公告)日：2021-09-16

申请号：US16819902

申请日：2020-03-16

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  John Paul Tellkamp

IPC: H01L23/495 ,  H01L43/04 ,  H01L21/48

Abstract: A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.

公开(公告)号：US20210305024A1

公开(公告)日：2021-09-30

申请号：US16828869

申请日：2020-03-24

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  John Paul Tellkamp

IPC: H01J37/32 ,  H01L21/02

Abstract: In a described example, a method includes loading at least one package substrate strip including electronic device dies mounted on the at least one package substrate strip into a plasma process chamber; positioning at least one E-field shield in the plasma process chamber spaced from and over the at least one package substrate strip; and plasma cleaning the at least one package substrate strip.

公开(公告)号：US10892405B2

公开(公告)日：2021-01-12

申请号：US16404978

申请日：2019-05-07

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R15/20 ,  H01L23/495 ,  G01R33/07 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US11658243B2

公开(公告)日：2023-05-23

申请号：US16566187

申请日：2019-09-10

Applicant: Texas Instruments Incorporated

Inventor： John Paul Tellkamp ,  Andrew Couch

IPC: H01L29/78 ,  H01L23/495 ,  H01L23/64 ,  H01F19/08 ,  H01L23/00

CPC classification number: H01L29/7846 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49503 ,  H01L23/49575 ,  H01L23/645 ,  H01L23/647 ,  H01F2019/085 ,  H01L23/49555 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012

Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

公开(公告)号：US11574884B2

公开(公告)日：2023-02-07

申请号：US17162189

申请日：2021-01-29

Applicant: Texas Instruments Incorporated

Inventor： Suvadip Banerjee ,  John Paul Tellkamp

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01R9/00 ,  H05K7/00 ,  B23K31/02 ,  H01L23/00 ,  H01L21/48 ,  H01L23/528 ,  H01L23/488

Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

公开(公告)号：US20140375350A1

公开(公告)日：2014-12-25

申请号：US13922428

申请日：2013-06-20

Applicant: Texas Instruments Incorporated

Inventor： John Paul Tellkamp

IPC: G01R31/28

CPC classification number: G01R31/129 ,  G01R31/2623 ,  G01R31/2862

Abstract: A method of testing an integrated circuit clearance distance device (“ICCDD”) having a predetermined clearance distance in air requirement and a predetermined isolation voltage limit including calculating a value of the breakdown voltage at the predetermined clearance distance for at least one gas; and selecting a gas in which the ICCDD has a breakdown voltage that is less than the predetermined isolation voltage.

Abstract translation: 一种在空气要求中具有预定间隙距离的集成电路间隙距离装置（“ICCDD”）和预定的隔离电压极限的方法，包括计算至少一种气体在预定间隙距离处的击穿电压值; 以及选择其中ICCDD具有小于预定隔离电压的击穿电压的气体。

公开(公告)号：US11569153B2

公开(公告)日：2023-01-31

申请号：US16819902

申请日：2020-03-16

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  John Paul Tellkamp

IPC: H01L21/48 ,  H01L23/495 ,  H01L43/04

Abstract: A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.