公开(公告)号：US12087673B2

公开(公告)日：2024-09-10

申请号：US17983249

申请日：2022-11-08

Applicant: Texas Instruments Incorporated

Inventor： Abram Castro ,  Usman Chaudhry ,  Joe Adam Garcia ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/67 ,  H01L23/31 ,  H05K1/18 ,  H05K3/34 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/67138 ,  H01L23/3121 ,  H01L23/49541 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3494 ,  H01L22/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/3511 ,  H05K2201/10636

Abstract: An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).

公开(公告)号：US20240194574A1

公开(公告)日：2024-06-13

申请号：US18585629

申请日：2024-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yogesh Kumar Ramadass ,  Salvatore Frank Pavone ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49589 ,  H01L23/4951 ,  H01L23/49524 ,  H01L24/32 ,  H01L24/73 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/16245 ,  H01L2224/32265 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

公开(公告)号：US12009336B2

公开(公告)日：2024-06-11

申请号：US17390823

申请日：2021-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahmud Halim Chowdhury ,  Amin Sijelmassi ,  Murali Kittappa ,  Anindya Poddar ,  Honglin Guo ,  Joe Adam Garcia ,  John Paul Tellkamp

IPC: H01L23/00 ,  H01H85/02 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L24/48 ,  H01H85/0241 ,  H01L24/49 ,  H01L24/85 ,  H01H2085/0283 ,  H01L23/49555 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/4801 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/4846 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/49111 ,  H01L2224/494 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/8534 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/2064 ,  H01L2924/2075

Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

公开(公告)号：US11031364B2

公开(公告)日：2021-06-08

申请号：US15914761

申请日：2018-03-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier ,  Sadia Naseem ,  Mahmud Halim Chowdhury

IPC: H01L23/00

Abstract: In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

公开(公告)号：US11676930B2

公开(公告)日：2023-06-13

申请号：US17315102

申请日：2021-05-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier ,  Sadia Naseem ,  Mahmud Halim Chowdhury

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L24/83 ,  H01L2224/32058 ,  H01L2924/35121

Abstract: In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

公开(公告)号：US20210265299A1

公开(公告)日：2021-08-26

申请号：US17315102

申请日：2021-05-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier ,  Sadia Naseem ,  Mahmud Halim Chowdhury

IPC: H01L23/00

Abstract: In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

公开(公告)号：US11021786B2

公开(公告)日：2021-06-01

申请号：US16209513

申请日：2018-12-04

Applicant: Texas Instruments Incorporated

Inventor： Luu Thanh Nguyen ,  Mahmud Halim Chowdhury ,  Ashok Prabhu ,  Anindya Poddar

IPC: H01L21/3205 ,  C23C14/12 ,  C23F11/10 ,  H01L21/288 ,  H01L21/768

Abstract: In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 μm on a surface of the copper corrosion inhibitor layer.

公开(公告)号：US11948871B2

公开(公告)日：2024-04-02

申请号：US17325197

申请日：2021-05-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yogesh Kumar Ramadass ,  Salvatore Frank Pavone ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49589 ,  H01L23/4951 ,  H01L23/49524 ,  H01L24/32 ,  H01L24/73 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/16245 ,  H01L2224/32265 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

公开(公告)号：US20230057405A1

公开(公告)日：2023-02-23

申请号：US17983249

申请日：2022-11-08

Applicant: Texas Instruments Incorporated

Inventor： Abram Castro ,  Usman Chaudhry ,  Joe Adam Garcia ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L23/31 ,  H05K1/18 ,  H05K3/34 ,  H01L21/48 ,  H01L21/67

Abstract: An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).

公开(公告)号：US20220375836A1

公开(公告)日：2022-11-24

申请号：US17325197

申请日：2021-05-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yogesh Kumar Ramadass ,  Salvatore Frank Pavone ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L23/00

Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.