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公开(公告)号：US20230205305A1
公开(公告)日：2023-06-29
申请号：US18060114
申请日：2022-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Chunhua Hu , Raghavendra Santhanagopal , Kazunobu Shin , Charles Gerlach , Rejitha Nair , Ritesh Sojitra , Sai Rajaraman , Anthony Seely , Siva Srinivas Kothamasu , Varun Singh , John Apostol
IPC: G06F1/3287 , G06F13/16 , G06F13/40 , G06F13/42
CPC classification number: G06F1/3287 , G06F13/1668 , G06F13/4068 , G06F13/423
Abstract: A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.
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公开(公告)号：US11662763B1
公开(公告)日：2023-05-30
申请号：US17537150
申请日：2021-11-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Varun Singh , Rejitha Nair , John Chrysostom Apostol , Venkateswar Reddy Kowkutla , Raghavendra Santhanagopal
Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.
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公开(公告)号：US20250015698A1
公开(公告)日：2025-01-09
申请号：US18897219
申请日：2024-09-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Kazunobu Shin , Venkateswara Pothireddy , Siva Kothamasu , John Apostol , Raghavendra Santhanagopal , Rajagopal Kollengode Ananthanarayanan , Rejitha Nair , Charles Gerlach , Ravi Teja Reddy
Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
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公开(公告)号：US11899563B2
公开(公告)日：2024-02-13
申请号：US17686348
申请日：2022-03-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F13/10 , G06F11/36 , G06F9/4401 , G06F11/30
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.
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公开(公告)号：US12271289B2
公开(公告)日：2025-04-08
申请号：US18403293
申请日：2024-01-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F9/44 , G06F9/4401 , G06F11/30 , G06F11/362 , G06F13/10
Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
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Patent Agency Ranking
公开(公告)号：US20150253387A1
公开(公告)日：2015-09-10
申请号：US14721216
申请日：2015-05-26
Applicant: Texas Instruments, Incorporated
Inventor： Anshul Gahoi , Raghavendra Santhanagopal , Pradeep Kumar Babu
IPC: G01R31/3177
CPC classification number: G06F11/27 , G01R13/28 , G01R31/3177 , G06F9/44 , G06F11/273 , G06F17/5027 , G06F17/5054
Abstract: A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.
Abstract translation: 基于可编程接口的验证和调试系统包括例如测试连接器，该测试连接器布置成将被测设备通信地耦合到测试夹具。 可编程逻辑接口通信地耦合到测试连接器并且被布置成接收可下载的测试台，其中可下载的测试台被布置为将测试向量从第一组测试向量应用到第一测试控制总线。 多路复用器被布置为选择性地将第一测试控制总线和第二测试控制总线中的一个耦合到耦合到测试连接器的共享测试总线，其中第二测试控制总线被布置成将测试向量从第二组 由例如由人操作的调试器提供的测试向量。
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公开(公告)号：US20150089289A1
公开(公告)日：2015-03-26
申请号：US14038743
申请日：2013-09-26
Applicant: Texas Instruments, Incorporated
Inventor： Anshul Gahoi , Raghavendra Santhanagopal , Pradeep Kumar Babu
IPC: G06F11/27
CPC classification number: G06F11/27 , G01R13/28 , G01R31/3177 , G06F9/44 , G06F11/273 , G06F17/5027 , G06F17/5054
Abstract: A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.
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公开(公告)号：US12132386B2
公开(公告)日：2024-10-29
申请号：US18160308
申请日：2023-01-27
Applicant: Texas Instruments Incorporated
Inventor： Venkateswar Kowkutla , Kazunobu Shin , Venkateswara Pothireddy , Siva Kothamasu , John Apostol , Raghavendra Santhanagopal , Rajagopal Kollengode Ananthanarayanan , Rejitha Nair , Charles Gerlach , Ravi Teja Reddy
CPC classification number: H02M1/0032 , H02M3/04
Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
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公开(公告)号：US20240134776A1
公开(公告)日：2024-04-25
申请号：US18403293
申请日：2024-01-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F11/36 , G06F9/4401 , G06F11/30 , G06F13/10
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
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公开(公告)号：US20230238872A1
公开(公告)日：2023-07-27
申请号：US18160308
申请日：2023-01-27
Applicant: Texas Instruments Incorporated
Inventor： Venkateswar Kowkutla , Kazunobu Shin , Venkateswara Pothireddy , Siva Kothamasu , John Apostol , Raghavendra Santhanagopal , Rajagopal Kollengode Ananthanarayanan , Rejitha Nair , Charles Gerlach , Ravi Teja Reddy
CPC classification number: H02M1/0032 , H02M3/04
Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
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