公开(公告)号：US09543374B2

公开(公告)日：2017-01-10

申请号：US14569975

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Greg Charles Baldwin ,  Kamel Benaissa ,  Sarah Liu ,  Song Zhao

IPC: G06F17/50 ,  H01L49/02 ,  H01L27/06 ,  H01L21/265 ,  H01L21/8238 ,  H02J7/02 ,  H02J7/00

CPC classification number: H01L28/22 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/0629 ,  H02J7/0044 ,  H02J7/025

Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Abstract translation: 一种将低TCR电阻添加到基准CMOS制造流程的方法。 在CMOS制造流程中形成低TCR电阻器的方法。 在CMOS制造流程中形成具有低TCR电阻器的n型和p型晶体管的方法。

公开(公告)号：US08940612B2

公开(公告)日：2015-01-27

申请号：US14074831

申请日：2013-11-08

Applicant: Texas Instruments Incorporated

Inventor： Kamel Benaissa

IPC: H01L21/20 ,  H01L27/06 ,  H01L29/43

CPC classification number: H01L27/0629 ,  H01L27/0288 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/435 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

Abstract translation: 可以通过形成第一多晶硅层并将其去除在薄多晶硅电阻器的区域中来形成包含金属栅极晶体管和薄多晶硅电阻器的集成电路。 第二层多晶硅形成在多晶硅的第一层上，并在多晶硅薄膜的区域中形成。 薄多晶硅电阻器形成在第二层多晶硅中，并且牺牲栅极形成在第一多晶硅层和第二多晶硅层中。 在第二多晶硅层上形成PMD层，并且去除PMD层的顶部，以暴露牺牲栅极，但不暴露薄多晶硅电阻器中的第二层多晶硅。 去除牺牲栅极并形成金属替换栅极。

公开(公告)号：US20170133366A1

公开(公告)日：2017-05-11

申请号：US15409893

申请日：2017-01-19

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L29/45 ,  H01L21/027 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

公开(公告)号：US09583609B2

公开(公告)日：2017-02-28

申请号：US13850192

申请日：2013-03-25

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract translation: 形成具有位于第一方向上的纵向轴线的细长金属接触，以形成与延伸的源极和漏极区域的电连接，纵向轴线处于第一方向，并且细长金属与位于第二方向的纵向轴线接触形成 电连接到细长的源极和漏极区域，其中纵向轴线位于第二方向，其中第二方向垂直于第一方向。

公开(公告)号：US20140284725A1

公开(公告)日：2014-09-25

申请号：US13850192

申请日：2013-03-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract translation: 形成具有位于第一方向上的纵向轴线的细长金属接触，以形成与延伸的源极和漏极区域的电连接，纵向轴线处于第一方向，并且细长金属与位于第二方向的纵向轴线接触形成 电连接到细长的源极和漏极区域，其中纵向轴线位于第二方向，其中第二方向垂直于第一方向。

公开(公告)号：US10128145B2

公开(公告)日：2018-11-13

申请号：US14220693

申请日：2014-03-20

Applicant: Texas Instruments Incorporated

Inventor： Kamel Benaissa ,  Amitava Chatterjee

IPC: H01L21/761 ,  H01L21/8234 ,  H01L29/8605 ,  H01L29/66 ,  H01L27/08 ,  H01L21/266 ,  H01L27/06

Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.

公开(公告)号：US09966373B2

公开(公告)日：2018-05-08

申请号：US15409893

申请日：2017-01-19

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L21/027

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

公开(公告)号：US09508708B2

公开(公告)日：2016-11-29

申请号：US14569932

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Kamel Benaissa

IPC: H01L27/06 ,  H01L27/11 ,  H01L27/02 ,  H01L49/02 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L27/0288 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/435 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

公开(公告)号：US08753941B1

公开(公告)日：2014-06-17

申请号：US13766437

申请日：2013-02-13

Applicant: Texas Instruments Incorporated

Inventor： Kamel Benaissa ,  Vijay K. Reddy ,  Samuel Martin ,  T Krishnaswamy

IPC: H01L21/336

CPC classification number: H01L21/82385 ,  H01L21/26586 ,  H01L21/823814 ,  H01L27/0617 ,  H01L27/0922 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit with a LV transistor and a high performance asymmetric transistor. A power amplifier integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming an integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming a power amplifier integrated circuit with an nmos core transistor and an nmos high performance asymmetric transistor, a resistor, and an inductor.

Abstract translation: 具有LV晶体管和高性能不对称晶体管的集成电路。 一种具有核心晶体管和高性能不对称晶体管的功率放大器集成电路。 一种用核心晶体管和高性能不对称晶体管形成集成电路的方法。 一种形成具有nmos核心晶体管和nmos高性能不对称晶体管，电阻器和电感器的功率放大器集成电路的方法。